The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

The overall objective of the IT2 project is to explore, develop and demonstrate technology options that are needed to realize 2nm CMOS logic technology extending the scaled Semiconductor technology roadmap to the next node in accordance to Moore’s law. These activities cover creation of Lithography equipment, new Processes & Modules and Metrology tools capable to create and deal with new 2nm node 3D structures, defect analysis, overlay and features. The topics addressed by the program relate to the ECSEL MASP 2019 Chapter 10; “Process Technology, Equipment, Materials and Manufacturing for electronic components and systems”, with emphasis on the following major challenge “the Extension of world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and “Developing Technology for heterogeneous System-on-Chip (SoC) Integration” of the ECSEL JU Annual Work Plan 2019. The relation of the IT2 project to world leadership regards the extension of the scaled semiconductor technology roadmaps and thereby maintain competence in advanced More Moore technology in Europe to support leading edge manufacturing. The relation of the IT2 project to the Developing Technology for heterogeneous System-on-chip Integration comes from activities regarding “System Scaling” in which technology is developed that enables wafer-to-wafer bonding creating 3D heterogeneous solutions with the aim to resolve performance limitations in power and data congestion. In regard to the annual work plan 2019, the IT2 project support the ECSEL JU objectives by contribution to the development of a strong and competitive Electronic Components and Systems (ECS) by involving many of the equipment and tool developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KLA along the value chain and knowledge institutes such as ARCNL, imec, PTB, TNO and TU/e. And by stimulating a dynamic ecosystem through through the involvement of SMEs like IBS, Recif, Reden and Unity.

In line with industry needs, Moore’s law, scaling in ITRS 2013, and ECSEL JU MASP 2017, the main objective of the TAPES3 project is to discover, develop and demonstrate lithographic, metrology, EUV mask technology, devices and process modules enabling 3nm node technology. This is planned with available EUV/NA 0.33 scanners, and with system design and integration of a new hyper NA EUV lithography tool to enable more single exposure patterning at 3nm to create complex integrated circuits. Process steps for 3D devices as alternative to the conventional FINFet will be explored for application in the 3nm node. The impact of the application of these so called 3D devices on circuit topology and logic design will be explored. During the development, specific challenges in metrology for the characterization of 3D devices will be assessed and metrology tools will be newly developed. The result will be demonstrated in the imec pilot line. The TAPES3 project relates to the ECSEL work program topic Equipment, Material and Manufacturing. It addresses and targets, as set out in MASP, the grand Challange of "More Moore Equipment and Materials for sub 10nm technologies" by exploring the requirements and solutions for the 3nm node. The project touches the core of the continuation of Moore’s law. Moreover, the cost aware development process will support the involved companies, and will place them in a preferred position over their worldwide competition. Through their worldwide affiliations, the impact of the TAPES3 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.