The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform. Additional developments will be performed for the integration of memory, power management, connectivity, hard security on the same chip. The project will also target the industrialization of the embedded Phase Change Memory (PCM) technology built on top of the FDSOI 28nm logic process pilot line. The development of the ePCM will be driven by the final application requirements as well as decreasing the power consumption. The alternative memory solutions will be also studied as they have different - and complementary - traits in such areas as read/write speed, power and energy consumption, retention and endurance, and device density and benchmarked with the ePCM and the conventional eFlash. Continued advances in materials, device physics, architectures and design could further reduce the energy consumption of these memories. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage. These activities encompass such developments as: technology enhancements for various specific application requirements such as wide temperature range and reliability, high security requests, high flexibility…, design enablment allowing first time silicon success, prototyping demonstrator products in the different application areas. In the WAKEMEUP project, new devices and systems will be developed by the application partners in automotive and secure based on FD-SOI and embedded digital technology to answer specific applications needs.

GENESIS, backed by Horizon Europe, aims to make semiconductor manufacturing sustainable, aligning with the European Green Deal, by minimizing environmental impact with eco-friendly innovations. [Objectives] GENESIS aims to replace harmful materials with safer options, improve waste management, and enhance the use and recyclability of scarce materials. [Innovations] GENESIS introduces innovations in three key areas: • Innovative materials: PFAS-free polymer and eco-friendly gas alternatives complying with EU regulations. • Waste & emissions monitoring: Cutting-edge sensors detect hazardous substances for efficient aqueous and gas waste elimination, reducing environmental and health risks. • Scarce material management: New integration technologies optimize material usage and initiate recycling of scarce materials like Gallium, Niobium, and silicon carbide. [Methodology] GENESIS employs four technical work packages to research sustainable material substitution, emission reduction, and resource management. This modular approach promotes scalability and integration with existing processes, fostering a circular economy in the semiconductor sector. Supervised by management work packages, it quantifies environmental efficiency and engages in dissemination to promote European technological achievements [Outcomes] The project targets a 50% cut in hazardous materials, 30% decrease in emissions and waste, and improved scarce material recyclability, boosting EU semiconductor sustainability and global competitiveness. [Impact] GENESIS supports EU's tech sovereignty and resilience through accurate monitoring and sustainable practices. It positions Europe as a leader in sustainable semiconductor tech, setting new standards for impact-oriented communication and dissemination.

Up to now two kinds of graphene membranes for gas filtration applications have been made: very selective membrane by adding graphene oxide on porous material or membrane with an excellent permeance due to the atomic thickness of CVD grown graphene decorated with nanometer size pore holes. GATES project aims at making the laboratory demonstration at a TRL level 4 of a new membrane made of CVD graphene that will be both highly selective (103) between H2 (He) and CO2, N2, O2, Ar gases and with a high permeance (10-5 mol m-2 s-1 Pa-1 ). The project concept lies on technological innovations on the device and pore holes realization. The developed processes will be compatible with a CMOS technology to insure manufacturability. The device fabrication will escape one of the roadblock of graphene technology, which is its transfer step after the growth of the Single Layer Graphene (SLG). This step is hard to industrialize, and induces many macroscopic defects that can degrade largely the yield of membrane production. The ambition of GATES is to develop and demonstrate a technology without transfer, CMOS compatible. Ultimately, two devices will be stacked to increases the selectivity by adding tortuosity. To achieve a very high selectivity, it is mandatory to have sub nanometer pore diameter. In GATES, initial pyridinic-N or pyrrolic-N vacancies on the SLG will be created by nitrogen doping using different plasma technologies. If needed, these vacancies will be further etched. An alternative approach, to be evaluated in GATES, is to make nano-pores by using heavy ions produced at GANIL (Grand Accélérateur National d'Ions Lourds) facility. In both cases, the shapes and pores size statistics will be evaluated by advanced TEM observations performed in the consortium. These statistics will be used as input parameters for the modelling of the membrane performances. Furthermore, other complementary characterization techniques, as Raman spectrometry and X-ray photoelectron spectroscopy (XPS), will be employed for having deep knowledge of the produced membranes. In the project the filtering properties of undoped, N-doped and functionalized nano-porous graphene will be modelled. Ultimately, double-layered functionalized graphene will be also modelled. This modelling work will support the experimental developments and will be used to define the optimum structure for the best permeability/selectivity ratio. GATES will also assess the porosity due to grain boundaries by simulating different local environments, e.g. pentagons-heptagons. The development of such a graphene membrane and its application to leak detection, will offer a significant innovative product for users by providing a highly portable/integrated device with a very short response time.

The overall objective of the PIn3S project is to realize Pilot Integration of 3nm Semiconductor technology. This covers Process Integration, creation of Lithography Equipment, EUV Mask Repair Equipment and Metrology tools capable to deal with 3D structures, defects analysis, overlay and feature size evaluation. Each of these objectives will be achieved by cooperation between key European equipment developers like; ASML, Zeiss, Thermo Fisher, Applied Materials, Nova, KTI involved with their suppliers, involvement of a strong knowledge network based on Universities of Germany, Heidelberg University Hospital, and the Netherland, TU Delft and the University of Twente, complemented with key Technology Institutes such as imec and Fraunhofer. The project addresses Section 15 “Electronics Components & Systems Process Technology, Equipment, Materials and Manufacturing”, Major Challenge 4 “Maintaining world leadership in Semiconductor Equipment, Materials and Manufacturing solutions” and Major Challenge 1 “Developing advanced logic and memory technology for nanoscale integration and application-driven performance” of the ECSEL JU Annual Work Plan 2018. As set out in the Multi Annual Strategic Plan 2018, PIn3S addresses the ambition for the European Equipment & Manufacturing industry for advanced semiconductor technologies to lead the world in miniaturization by supplying new equipment and materials approximately two years ahead of introduction of volume production of advanced semiconductor manufacturers. With the results of the Pin3S project the consortium builds on realizing IC manufacturers to migrate to the 3nm Technology node which enables a class of new products which have more functionality, more performance and are more power efficient. As such it will form the bases for innovations yet to come enabling solutions that address the societal challenges in communication, mobility, health care, security, energy and safety & security.

The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt. The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the support technology to demonstrate the high performances path as well as the robustness of the ePCM solution. The next generation of FDSOI ePCM will be main path for general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security. On top of the development and industrialization of silicon process lines and SoC design, storAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.