Shared-memory multi-core processors are ubiquitous, but programming them remains challenging. The programming model exposed by such multi-core processors depends crucially on a "memory consistency model" (MCM), a contract between the hardware and the programmer, which essentially specifies what value a read can return. On the hardware side, one key mechanism to implement the memory consistency model is the "cache-coherence protocol" (CCP), which essentially communicates memory operations between processors. However, the connection between the CCP and the MCM remains unclear. This is especially true for modern CCPs and MCMs, in which CCP design has been divorced from the requirements of the MCM. We argue that this has negatively impacted the scalability and the verifiability of CCPs. On the scalability front, there are serious question marks about sustaining cache coherence as the number of cores continue to scale. On the verification front, the application of existing verification techniques, which do not verify the CCP against the MCM, are arguably broken. In the C3 proposal, we propose a family of CCPs that are "aware" of, and verified against the MCM. Our approach is motivated by the fact that both hardware and programming languages are converging to various relaxed MCMs for performance oriented reasons. We use such relaxed MCMs as inspiration to research CCPs that can take advantage of them. Specifically, we will research "lazy" CCPs where memory operations are batched, and the cost of communicating a memory operation can be amortised. We will also, for the first time, formally verify the relationship between the hardware CCPs and the programmer-oriented MCM they provide. We will investigate rigorously the gains to be had from such lazy CCPs. We will do this by creating a multi-core silicon prototype of our proposed CCP, leveraging our experience in the design of industrial-strength micro-architectures and their implementations.

High speed data communication underpins many important facets of modern life. High speed internet, online learning, high-definition video streaming, cloud computing, video conferencing, online gaming, artificial intelligence and the inner works of computers themselves all rely on the ability to transfer vast quantities of data at high speed. With the continuous introduction of increasing advanced and data hungry applications, the demand for bandwidth has grown relentlessly and is set to continue into the future. As data transmission rates increase so does power consumption and in some cases can dominate the power usage of the entire computing system. The growth of power use in the ICT industry is a major global concern with predictions showing that it could account for 20% of electricity usage worldwide and emit up to 5.5% of the world's carbon emissions by 2025. To support the growth in data demands it is of paramount importance that data communication technology is able to keep pace whilst minimising power use. Communication links are continuously being converted from working in the electrical domain to the optical domain since much more data can be transmitted optically with lower power consumption. The conversion is moving to progressively shorter links as the available technology becomes more cost effective and electrical bandiwdth limits are reached. Silicon photonic technology has been a key enabler of the conversion particularly in the data centre application space since the technology allows production of integrated photonics transceiver chips in a reliable, low-cost CMOS (Complementary metal-oxide-semiconductor) manner. Within the optical transmission link the process of converting electrical data into an optical format typically dominates power consumption. It is performed either by using an external optical modulator or by directly modulating the laser and for shorter optical links to be viable, their power usage must be reduced. For example, after almost two decades of research the performance of the silicon based optical modulator has manged to reach 100Gbaud with 1 pj/bit power consumption (including drive and tuning power), but power requirements for off chip and on chip links are ~100fJ/bit and 10fJ/bit respectively. For silicon photonic data transmission technology to meet these stringent energy and bandwidth requirements the hybrid integration of materials with stronger electro-optic effects onto silicon is essential as this will allow vast reductions in power consumption. In this proposal, we apply an advanced geometrically defined crystal growth process, tunnel epitaxy, to grow III-V semiconductors onto silicon photonic chips for use in a new-generation of optical modulation technology. The approach offers unique advantages in terms of footprint, yield, material quality and the ability to laterally grade doping levels during the growth process allowing precise optimisation of the trade-off between device bandwidth and optical loss. Combining the strength of the silicon photonics expertise at Southampton and the III-V on Si manufacturing at Cardiff, we will design and fabricate both external optical modulators and directly modulated light sources with state-of-the-art performance, targeting both short and ultra-short data reach applications. We will produce devices with 100Gbaud transmission with order of magnitude improvement in drive power which will enable the next generation of ultra short links to be viable. The developed technology will positively impact a large range of applications providing wide reaching societal and economic benefits.

As our software systems grow in size and complexity, increasingly diverse users have different wants and needs from their languages: the right language for a statistician (e.g. R) is different from that of someone who formally verifies safety properties (e.g. OCaml), which is different again from someone creating user-facing apps (e.g. Javascript). However, different languages inhabit different silos and interactions between them are crude and slow. Language composition has long been touted as the solution to this problem, allowing languages to be used together in a fine-grained way, but has traditionally struggled to match this promise. In the Lecture Fellowship, my team and I showed that large, messy, real-world languages can be composed together, even allowing different languages to be intermingled within a single line of code. We were able to make the performance of such multi-lingual programs close to their mono-language constituents, showing that language composition's promise is real. However, in the course of this research, an unexpected problem became apparent: Virtual Machines (VMs), the systems used to make many languages run fast (and which are crucial to the good performance of language composition), do not perform as expected. In the largest VM experiment to date, we showed that VMs perform incorrectly in around 60% of cases. Attempts to fix existing VMs have largely failed, because the problems are so deeply embedded that they cannot be teased out, even after careful examination. This is a significant problem for language composition, for which VMs are a foundational pillar. This Fellowship Extension thus aims to show that VMs can have good, predictable performance and that they are a suitable foundational pillar for language composition. However, we cannot expect to create a traditional VM, which often consume tens, hundreds, or thousands of person years of effort. Instead, my team and I will create a new meta-tracing VM system, since history shows that these can be created in a small number of person years. Fortunately for us, meta-tracing has also been shown as the fastest way to run multi-lingual programs, so it is a natural fit. We will rigorously benchmark the new meta-tracing system we create from the beginning of, and throughout, its development. This will enable us to observe performance regressions soon after they occur, allowing us to fix them quickly. We will also take the opportunity to address one of meta-tracing's biggest weaknesses: its slow warmup, that is the time between a program starting, and JIT compilation completing. Tracing currently involves a software interpreter interpreting a software interpreter, with a 100-200x overhead when a loop is traced. We will use the Processor Trace (PT) feature found in recent x86 chips to move the software part of meta-tracing into hardware, giving a roughly 100x speed-up to this critical phase of the system. That will also allow us to be more aggressive in optimising other parts of the tracer that currently cause poor warm-up. At the end of this Fellowship Extension, alongside traditional research papers, we will produce an open-source release of our new meta-tracing system. This will allow others to build on our work, be that for language composition, or simply to make individual languages run fast.

The aim of this project is to develop a unified scheme cooperative multi-modal and multi-sensor tracking. The multi-sensor network will be composed of stereo microphones coupled with omni-directional and with pan-tilt-zoom cameras. Sound information will be used to discriminate ambiguous visual observations as well as to extend the coverage area of the sensors beyond the field of view of the cameras. Although single modality as well as multi-modality trackers have achieved some success, a number of important tracking issues remain open for enabling the adoption of these algorithms in real-world scenarios. Among these issues, three important inter-related problems will be addressed in this project, namely the definition of a generic and flexible feature representation for a target, a reliable mechanism to update the target model based on incoming observations, and a robust multi-sensor handover strategy. First, we will develop a robust and adaptive representation of objects based on their acoustical and visual attributes while moving across the network of heterogeneous sensors. Next, object models will be defined based on the observation that temporal representation of a target is expected to lie in a low-dimensional manifold in the high-dimensional multi-modal feature space. Finally, the object model will be used to control and guide the evolution of the target state in order to help intra-sensor occlusion handling and inter-sensor handover. To evaluate the tracking scheme, we will create a test corpus and its associated ground-truth data for use in the project as well as for distribution to the research community to facilitate comparisons.

Current wireless systems, from Wi-Fi to 5G, have been designed by following principles that have not changed over the last 70 years. This approach has given us dependable, universal wireless connectivity solutions that can deliver any type of digital information. As computing systems substitute universal digital processors with specialised circuits for artificial intelligence (AI), and as wireless connectivity becomes an integral part of the sensing-compute-actuation fabric powered by AI, it is essential to rethink the fundamental principles underpinning the design of wireless systems. The global telecom market is estimated at around USD 850 billion, with the UK telecom industry generating around GBP 30 billion in 2020. The countries that will lead in the creation of the new technological principles and capabilities underpinning 6G will have a significant international market edge, making fundamental research on the subject a critical national policy issue. In this context, neuromorphic sensing and computing are emerging as alternative, brain-inspired, paradigms for efficient data collection and semantic signal processing that build on event-driven measurements, in-memory computing, spike-based information processing, reduced precision and increased stochasticity, and adaptability via learning in hardware. The neuromorphic sensing and computing market was valued at USD 22.5 million in 2020, and it is projected to be worth USD 333.6 million by 2026. Current commercial use cases of neuromorphic technologies range from drone monitoring to the development of fast and accurate COVID-19 antibody testing. NeuroComm views the emergence of neuromorphic technologies as a unique opportunity for the development of efficient, integrated wireless connectivity and semantic processing -- referred to broadly as wireless cognition. Specifically, NeuroComm aims systematically addressing the integration of neuromorphic principles within an end-to-end system encompassing sensing, computing, and wireless communications. The informational currency of neuromorphic computing is not the bit, but the timing of spikes. Neuroscientists have long studied the efficiency and effectiveness of spike-based communications in biological neurons. In the context of wireless cognition, spike-based processing and communication raise novel fundamental questions regarding optimal joint signaling and computing strategies. NeuroComm will take the approach of starting from first, information-theoretic, principles, addressing the problem of what to implement before investigating how to best deploy neuromorphic based wireless cognition. To this end, the project aims at developing an information-theoretic framework for the analysis of wireless cognition systems with neuromorphic transceivers. The efficiency of neuromorphic computing hinges on the co-design of hardware and software. NeuroComm posits that a close integration of neuromorphic computing and communications at the design stage will be needed in order to fully leverage the benefits of brain-inspired wireless cognition. NeuroComm is a collaboration between King's College London (KCL) as lead institution and Princeton University (PU) as academic partner, along with NVIDA, Intel Labs, AccelerComm, and IBM Zurich as industrial partners. The research will build on the PIs' expertise in information theory, machine learning, communications, and neuromorphic computing to explore theoretical foundations, algorithms, and hardware implementation.