Developing new security paradigms, architectures, and software, for more secure and trustworthy ICT systems and services has clear social, scientific, and market motivation. This motivation is becoming stronger due to the changing threat landscape; over the past decade we are witnessing an ever-increasing amount of cyberattacks on the Internet. We believe that to advance the field of cybersecurity, we must act proactively and in synergy, instead of being reactive to cyberattacks. We propose SHARCS, a framework for designing, building and demonstrating secure-by-design applications and services, that achieve end-to-end security for their users. SHARCS will achieve this by systematically analyzing and extending, as necessary, the hardware and software layers in a computing system. This holistic approach is necessary, as no system can truly be secure unless every layer is secured, starting from the lowest one. We will measure the effectiveness of the SHARCS framework by using it on a diverse set of security-critical, real-word applications. The applications have been chosen from three different domains, medical, cloud and automotive, to demonstrate the platform independence capabilities of SHARCS. SHARCS will provide a powerful foundation for designing and developing trustworthy, secure-by-design applications and services for the Future Internet.

VINEYARD will develop an integrated platform for energy-efficient data centres based on new servers with novel, coarse-grain and fine-grain, programmable hardware accelerators. It will, also, build a high-level programming framework for allowing end-users to seamlessly utilize these accelerators in heterogeneous computing systems by using typical data-centre programming frameworks (e.g. MapReduce, Storm, Spark, etc.). VINEYARD will develop two types of energy-efficient servers integrating two novel hardware accelerator types: coarse-grain programmable dataflow engines and fine-grain all-programmable FPGAs that accommodate multiple ARM cores. The former will be suitable for data centre applications that can be represented in dataflow graphs while the latter will be used for accelerating applications that need tight communication between the processor and the hardware accelerators. Both types of programmable accelerators will be customized based on application requirements, resulting in higher performance and significantly reduced energy budgets. VINEYARD will additionally develop a new programming framework and the required system software to hide the programming complexity of the resulting heterogeneous system based on the hardware accelerators. This programming framework will also allow the hardware accelerators to be swapped in and out of the heterogeneous infrastructure so as to offer efficient energy use. VINEYARD will foster the expansion of the soft-IP cores industry, currently limited in the embedded systems, to in data centre market. The VINEYARD consortium has strong industrial foundations, and covers the whole value chain in the data-centre ecosystem; from the data-centre vendors up to the data-centre application programmers. VINEYARD plans to demonstrate the advantages of its approach in three real use-cases a) a bioinformatics application for high-accuracy brain modelling, b) two critical financial applications and c) a big-data analysis application.

The vision of SDK4ED is to minimize cost, time and complexity of low-energy software development processes, by providing tools for automatic optimization of both software quality and non-functional requirements such as energy efficiency, dependability and performance, with the capacity to tackle the interplay between design quality and run-time constraints. SDK4ED aims to realise its vision through the following objectives: - establish a set of methods and tools for monitoring processes for early identification of design flaws, energy consumption indicators, and security vulnerabilities, with respect to the targeted hardware platform and non-functional requirements - estimate the costs and limitations associated to technical debt (TD) liabilities in the entire software stack - provide toolboxes for assessing project management decisions with respect to the choices of repaying TD, under the constraints imposed on energy consumption and security - deploy the envisaged solutions in three industry-driven distinctive but complementary use cases in the domains of airborne systems, healthcare, and automotive industry - Illustrate the importance and benefits introduced by proper TD management into low-energy software application development - train and consult the embedded software systems industry. Through its envisaged toolboxes, SDK4ED will comprise a set of software programming add-ons for preventing the degradation of run-time qualities and especially energy consumption, while allowing for efficient measuring of the accumulated TD during the development of new low-energy computing software applications, including embedded systems and IoT products. The major expected impact of the proposed platform will be measured by the achieved improvement in productivity, the extent to which the envisaged tools will be adopted by the reference market and the minimisation of effort for adopting digital technologies into low-energy products and services.

To achieve the demands of extreme scale and the delivery of exascale, we embrace the computing platform as a whole, not just component optimization or fault resilience. EuroEXA brings a holistic foundation from multiple European HPC projects and partners together with the industrial SME focus of MAX for FPGA data-flow; ICE for infrastructure; ALLIN for HPC tooling and ZPT to collapse the memory bottleneck; to co-design a ground-breaking platform capable of scaling peak performance to 400 PFLOP in a peak system power envelope of 30MW; over four times the performance at four times the energy efficiency of today’s HPC platforms. Further, we target a PUE parity rating of 1.0 through use of renewables and immersion-based cooling. We co-design a balanced architecture for both compute- and data-intensive applications using a cost-efficient, modular-integration approach enabled by novel inter-die links and the investigation of a custom EuroEXA processing unit with integration of FPGA for data-flow acceleration. We provide a homogenised software platform offering heterogeneous acceleration with scalable shared memory access and create a unique hybrid geographically-addressed, switching and topology interconnect within the rack while enabling the adoption of low-cost Ethernet switches offering low-Latency and high-switching bandwidth. Working together with a rich mix of key HPC applications from across climate/weather, physics/energy and life-science/bioinformatics domains we will demonstrate the results of the project through the deployment of an integrated and operational peta-flop level prototype hosted at STFC. Supported by run-to-completion platform-wide resilience mechanisms, components will manage local failures, while communicating with higher levels of the stack. Monitored and controlled by advanced runtime capabilities, EuroEXA will demonstrate its co-design solution supporting both existing pre-exascale and project-developed exascale applications.