Counterfeit products, particularly cloning of different electronics devices, are emerging as a significant problem in many industries and technologies. One way to approach this problem is to create Physical Uncloneable Functions (PUFs). They are a relatively recent invention providing an alternative method to generate secrets for unique identification or cryptographic key generation. Instead of storing the secret in digital memory, or asking a user to provide it, it is derived from a physical characteristic of the system. The assumption is that the secret cannot be copied, as it is bound to a physical entity which cannot be cloned. Furthermore, it is assumed that the probability of finding two devices with identical physical characteristics is very low. Hence, using this atomistic variability could create unique fingerprints which can be used to securely and precisely identify a specific device or an object. As a result, PUFs have the potential to revolutionise the way that resource-constrained (e.g. IoT) devices are authenticated. When compared to existing solutions they offer small footprints, use fewer resources and provide much greater security. Existing demonstrations of PUFs have been limited, however, and results are constrained by statistics. A lack of validation through large-scale testing or simulations is a significant barrier to adoption. Hence, one of the aims of this proposal is to address this issue. In this fellowship, two possible structures will be explored as a PUF: a Resonant Tunnelling Diode (RTD) and a Single Electron Transistor (SET). Both devices encapsulate a quantum nanostructure. RTDs and SETs display an exotic I-V characteristic not seen in classical devices, with the nanostructure only allowing electrons to exist at well-defined energy levels. Current can only flow through the device at these energies, thus, this type of devices allows current to flow only at well-defined voltages. These voltage peaks are highly dependent on the quantum confinement exhibited within the nanostructure, which is subject to the overall atomic arrangement of the device. Hence, the device output is directly linked to atom-scale variations and could be used as unique 'fingerprints' to distinguish each device. Moreover, the devices at the heart of this proposal (RTD and SET) are compatible with the current CMOS technology. It can be manufactured from a wide range of materials, at different scales and in different configurations. However, finding the optimal design for incorporation into existing fabrication processes by trial and error would be time consuming and expensive. This is a significant barrier to exploitation of those devices. Hence, the other aim of this fellowship is to overcome this significant barrier by combining theory and simulations with experiments, addressing fundamental issues and providing insight that leads to improvement of the fabrication processes. This project brings together three UK company and one research groups in the University of Glasgow to deliver progress in the field of improving the design parameters and performance of RTDs and SETs for a specific PUF application.

Flash memories are used to store phone numbers, music, pictures and videos in mobile phones and are also frequently now used in place of magnetic hard disks in laptop computers. Such memories are non-volatile retaining information even if a battery looses all charge. Consumers constantly want more memory on their portable electronic devices to allow more video and music to be stored but flash memory is already close to the scaling limits preventing significant increases to memory sizes in the future. A flash memory consists of a floating gate charge node where the a single bit of digital information is stored as a "1" when the node is charged and "0" when the node is discharged. As the floating gate is reduced in size, there are more errors when electrons leak out of or onto the floating gate. These errors result from variation in floating gate size by just a few atomic layers which are sufficient to substantially change the applied voltage required to tunnel electrons onto or off the floating gate. This limit has been reached with present production. Our approach to improve flash memory and allow smaller memories is to use molecules which are produced chemically to allow charges to be stored as the digital memory and as the molecules are all identical, they do not suffer the same variability errors as the present silicon floating gate flash memories. Out ultimate aim is to use single molecules to enable further scaling thereby aiming to increase the amount of memory available in the future. We will also investigate molecules that can store more than "0" and "1" known as multi-valued memory. This multi-valued memory approach allows more bits to be stored on a single floating gate thereby allowing higher memory density expanding further what could be stored on a mobile phone or laptop computer. The approach we are taking requires the ability to measure the state an electron occupies on a single molecule. Therefore the technique developed here could be used to measure the properties of single molecules. This has potential applications for measuring the electronic properties of single molecules directly allowing the full characterisation of the molecular levels which at present is difficult to achieve. We believe these techniques can benefit a wide range of researchers in chemistry, physics, materials science and engineering in achieving far cheaper characterisation of materials at the nanoscale.

For future ICT industry, the elephant in the room is Internet of Things (IoT) and Artificial Intelligence (AI). They are driving the fourth industrial revolution that is profoundly changing how we live and interact. The main issues for IoT and AI have been identified as: power, security, and cost. This project is co-created with the industrial partners and focuses on the power issue. One of the most effective way for reducing power is by lowering the operation voltage, Vg, towards the transistor threshold voltage, Vth. This has motivated recently extensive research in near threshold voltage computing. As Vg approaches Vth, the operation window (Vg-Vth) reduces and the system will be increasingly vulnerable to instability in Vth: a small rise in Vth can effectively switch off a transistor. Instability causes faults in operation, such as read and write errors in SRAM and digital timing errors. It is a limiting factor for how low (Vg-Vth) and, in turn, how much power consumption can be reduced. One of the critical tasks for low power system optimization is to minimise operation voltage and power consumption that will deliver specified yield 'Y' in 'X' years at a temperature below 'T'. To complete this optimization, designers need a fault analysis model that gives the time evolution of the probability distribution of Vth and driving current, Id, at a given distance from their target values. The further Vth and Id depart from their target values, the more likely a circuit will fail. Despite of decades of research, a reliable fault model is still not available. Indeed, in a recent review, the lack of realistic fault model tops the list of challenges for Cognitive Computing System design. Although the need for this model is clear, even world-leading EDA suppliers and foundries cannot deliver the model and current SPICE models simply do not include Jitter. This is related to weaknesses of previous research, including statistically inconsistent bottom-up methodology, limited time window, weak model verification criterion, and the neglect of the interaction of different instability sources. The fabless UK IC-design companies are using foundries for their chip fabrication. Software is the essential bridge between designers and foundries. As there are no generally accepted realistic fault models at present, designers have to rely on adding a guard-band (design margins) obtained from empirical 'worst case guess'. This contributes to the substantial discrepancy between design and Si performance. As CMOS nodes are downscaled to nano-meter range, the stochastic spreading of device parameters increases dramatically this discrepancy, which has been identified as a major challenge for optimizing the design of low power IoT and Cognitive Computing Systems. The aim of this project is to provide the world first test-proven fault model that enables statistical, dynamic, and quantitative analysis of fault rate and in turn the optimization of low power IoT and Cognitive Computing Systems. Novel techniques and methodologies will be employed to overcome the weakness of early works, including a top-down approach to remove device selection, advanced data acquisition method for long time window, qualifying the model by prediction capability, covering the interactions between different sources of instabilities. The developed model will be tested against Si performance of real circuits together with the industrial project partners. If successful, it will deliver a paradigm shift from one-size-fit-all to application specific fault analysis and optimization, reducing power and time-to-market.

Quantum computers are superior to conventional computers for their high computing power, and this is true only if they have many qubits e.g., 100s or more. The current leading commercial players in the field have successfully demonstrated processors with more than 50 cryogenic qubits using the classical control interferences which suffer from bulky cables and electronics. Novel solutions are desperately and urgently required for qubit upscaling. Avenues for improvement include dramatically increasing the number, density and modularity of independent control channels, signal bandwidth, the time and amplitude resolution of generated waveforms, and the physical footprint of circuits and interconnects for noisy intermediate-scale quantum computing (NISQC), universal fault-tolerant quantum computing (UFTQC) and efficient multiplexing of single-photon detectors. This project will be a step towards improving the performance of and potentially revolutionising QC control hardware and future integration based on modern information and communication hardware. This will be achieved by synergising QC with ICT's state-of-the-art developments in optical, wireless and cyro-CMOS electronics. The researchers from both QC and ICT sectors will collaboratively identify, explore, develop, and benchmark the technologies at both device and system levels. Through nationwide networking chaired by NQCC with support from the University of Glasgow (UoG), National Quantum Computing Centre (NQCC), National Physical Laboratory (NPL), University College London (UCL), University of Strathclyde (UoS), and Science and Technology Facilities Council (STFC) and more than 20 industrial and academic partners, we will eventually deliver the ambitious objectives for the next generation of quantum computers with more than 100 qubits. The first 12 months of EPIQC will be dedicated to co-creation activities aimed at validating and further refining the focus of our work. The NQCC will devote a project manager to coordinate and support the co-creation activities, helping to reach the broader community and ensuring activities are delivered professionally. In the first instance, a series of one-to-one conversations will be held with end-users to validate needs and understand the market pull. This will inform further one-to-one discussions with key industry players and the identification of supply chains and pre-competitive areas of research. This groundwork will be essential to the successful set-up and definition of a series of focus groups on each of the pillars, exploring state-of-the-art, future trends and markets and defining top-level roadmaps for pre-competitive challenges. These challenges will be further explored through sandpits defining the details of research strands under each pillar. In years 2-4 EPIQC focusses on investigations of cross-disciplinary interfacing and integration of alternative control and readout architectures through three complementary pillars, and the verification of ICT-QC hardware for user needs.