Interconnects impose major limits on the performance on integrated circuits during the exponential reduction of feature size of microchips. The semiconductor industry faces challenges in the metallization of interconnects below the 10 nm half pitch and is looking to alternative metallization schemes to replace copper, the traditional choice for the last 20 years, which no longer meet the conductivity requirements at decreasing length scales. Binary metals such as nickel-aluminium (NiAl) have been identified as a promising candidate that performs well with respect to resistivity at critical dimensions (sub-10 nm) to replace copper. However, there are several challenges associated with the instability of these materials regarding surface oxidation, leading to performance degradation. The objective of CRIME is the in-situ removal of the surface oxide and in-situ passivation of binary intermetallic compounds to prevent surface oxidation at the sub-10 nm half pitch for interconnect applications. To meet the future size requirements of interconnects, the downscaling of the cleaning and passivation processes from blankets to sub-10 nm half-pitch and the formation of patterned lines, with the aim of sub-7 nm half-pitch, will be performed. This will be achieved through an interdisciplinary approach that combines material science, chemistry, chemical engineering, nanoelectronics, and physics, to test different metal oxide removal and surface cleaning chemistries in combination with organic and inorganic passivation layers in-situ to overcome the formation of an oxide top layer. The passivation layers will be deposited in the liquid and vapour phase and various analytic techniques will be used to elucidate the surface chemistry and surface reaction mechanisms. CRIME goes beyond the state-of-the-art as the cleaning and passivating process and the downscaling of these processes on NiAl at the nanoscale and for advanced microelectronics nodes has not been previously demonstrated

The HPC Digital Autonomy with RISC-V in Europe (DARE) will invigorate the continent’s High Performance Computing ecosystem by bringing together the technology producers and consumers, developing a RISC-V ecosystem that supports the current and future computing needs, while at the same time enabling European Digital Autonomy. DARE takes a customer-first approach (HPC Centres & Industry) to guide the full stack research and development. DARE leverages a co-design software/hardware approach based on critical HPC applications identified by partners from research, academia, and industry to forge the resulting computing solutions. These computing solutions range from general purpose processors to several accelerators, all utilizing the RISC-V ecosystem and emerging chiplet ecosystem to reduce costs and enable scale. The DARE program defines the full lifecycle from requirements to deployment, with the computing solutions validated by hosting entities, providing the path for European technology from prototype to production systems. The six year time horizon is split into two phases, enabling a DARE plan of action and set of roadmaps to provide the essential ingredients to develop and procure EU Supercomputers in the third phase. DARE defines SMART KPIs for the hardware and software developments in each phase, which act as gateways to unlock the next phase of development. The DARE HPC roadmaps (a living document) are used by the DARE Collaboration Council to maximize exploitation and spillover across all European RISC-V projects. DARE addresses the European HPC market failure by including partners with different levels of HPC maturity with the goal of growing a vibrant European HPC supply chain. DARE Consortium partners have been selected based on the ability to contribute to the DARE value chain, from HPC Users, helping to define all the requirements, to all parts of the hardware development, software development, system integration and subsequent commercialization.

The project global goal is to develop an efficient, robust, and accurate model to simulate e-ECS under the Dymola/Modelica framework based on libraries provided by the Topic Manager. The central focus is placed on the major challenges underlined in the Clean Sky 2 MALET project which include the efficient simulation of the Vapor Compression System (VCS), the VCS heat exchangers, and the electrical components. The project modelling approach is twofold as both physical and surrogate models must be developed and integrated into the Dymola/Modelica framework. The TwinECS specific objectives are summarized as follows: • Development of thermo-fluid models: VCS heat exchangers and their successful integration in assembled VCS models. • Development of electrical models for: motor, power inverter, ATRU, IGBT and MOSFET. • Development of surrogate models of the aforementioned thermo-fluid and electrical components based on data analytics technics. • Simulation of a complete thermo-fluid-electrical VCS model using both the standard and the surrogate models.