As the fabrication dimensions of devices have reduced, the variability of their electrical parameters has increased. This effect can lead to circuit failure, particularly for low-power circuits designed in very small geometry processes. This problem may result in the potential of processes with 45 nm, 22 nm Leff and below not being fully realised. Current cell designs, such as those for SRAM cells have failure rates for the random fluctuations envisaged at 22nm that make large SRAM arrays unviable, and other cells have timing variations which force the clock rate to be unacceptably slow. This three-year proposal aims to develop techniques to develop robust cell circuits, and to develop design tools and techniques for circuits which will deliver the reliability and performance necessary in cell libraries for future multi-billion-transistor SoC.The main goals of the project are: (1) Evaluate circuit design tools for cell design in the face of severe and random process fluctuations, (2) Show how these tools can be improved to assist circuit designers achieve higher productivity, (3) Design more robust integrated circuits capable of good performance in nanometre technologies, with low supply voltages and large parameter fluctuations, (4) Derive general principles for robust cell design in nanometre processes, and to evaluate them in a realistic demonstrator

Designing chips in deep-sub micron technologies is becoming increasing difficult. Parameter variations in fabrication processes mean that pre-determining a safe operating clock-rate is often over cautious. Self-timed circuits eliminate the global controlling clock in favour of circuits which are self-timed and which operate in response the availability of valid data. In the past, the design of such circuits has been difficult but in the last 10 years, great advances have been made in tools for the automatic synthesis of self-timed circuits. However, these automatic tools are best suited to control circuits or to low performance systems.This work will develop novel algorithms for the automatic synthesis of self-timed datapaths and will embed these tools in a framework that will allow a designer to choose from a variety of self-timed implementation design styles. A designer will be able choose from a range of implementations / from those that are completely insensitive to delays within components to those which are aggressively-timed using relative timing constraints based on actual layout parameters. Design-for-test techniques and relative timing constraints will be fully exploited by incorporating them into the datapath architecture. The focus of the proposed research will be the automated generation of self-timed datapath structures such as pipelines and low-latency combinational blocks targeted at standard cell libraries.

Designing chips in deep-sub micron technologies is becoming increasing difficult. Parameter variations in fabrication processes mean that pre-determining a safe operating clock-rate is often over cautious. Self-timed circuits eliminate the global controlling clock in favour of circuits which are self-timed and which operate in response the availability of valid data. In the past, the design of such circuits has been difficult but in the last 10 years, great advances have been made in tools for the automatic synthesis of self-timed circuits. However, these automatic tools are best suited to control circuits or to low performance systems.This work will develop novel algorithms for the automatic synthesis of self-timed datapaths and will embed these tools in a framework that will allow a designer to choose from a variety of self-timed implementation design styles. A designer will be able choose from a range of implementations / from those that are completely insensitive to delays within components to those which are aggressively-timed using relative timing constraints based on actual layout parameters. Design-for-test techniques and relative timing constraints will be fully exploited by incorporating them into the datapath architecture. The focus of the proposed research will be the automated generation of self-timed datapath structures such as pipelines and low-latency combinational blocks targeted at standard cell libraries.

See Joint Proposal D232208

Biological brains are highly complex systems whose underlying principles of operation are little understood. We know that they comprise very large numbers of nerve cells - neurons - that interact with each other principally through electrical impulses or spikes, and we have instruments that can show which areas of the brain are more or less active at any time, but we know little about the intermediate levels of brain function. How, for example, are all the details of a complex visual scene encoded in the patterns of neural spikes in the visual cortex? And how do we use those patterns to recognize our family and friends?One way to help understand complex systems is to develop hypotheses of how those systems might work and then to use computers to test those hypotheses. Modelling spiking neurons is computationally very intensive, so a modern PC is capable of modelling a few tens of thousands of neurons in real time using a rather simple model of each neuron. In this research we plan to build a new sort of computer designed specifically for modelling large numbers of neurons in real time. This computer will be based upon large numbers of fairly simple microprocessors that communicate with each other using spike events modelled closely on the way biological neurons communicate. We will use developments in semiconductor technology to enable many microprocessors to be put on a single silicon chip, thereby keeping the cost and power consumption of the computer as low as possible.Our brains keep working despite frequent failures of their component neurons, and this fault-tolerant characteristic is of great interest to engineers who wish to make computers more reliable. So this work has two complementary ultimate goals: to use the computer to understand better how the brain works at the level of spike patterns, and to see if biology can help us see how to build computer systems that continue functioning despite component failures.