Crystalline silicon wafer solar cells have been dominating the photovoltaic market so far due to the availability and stability of c-Si and the decades of Si technology development. However, without new ways to improve the conversion efficiencies further significant cost reductions will be difficult and the c-Si technology will not be able to maintain its dominant role. In the SiTaSol project we want to increase conversion efficiencies of c-Si solar cells to 30 % by combining it with III-V top absorbers. Such a tandem solar cell will result in huge savings of land area and material consumption for photovoltaic electricity generation and offers clear advantages compared to today’s products. The III-V/Si tandem cell with an active Si bottom junction with one front and back contact is a drop-in-replacement for today’s Si flat plate terrestrial PV. To make this technology cost competitive, the additional costs for the 2-5 µm Ga(In)AsP epitaxy and processing must remain below 1 €/wafer to enable module costs <0.5 €/Watt-peak. It is the intention of the SiTaSol project to evaluate processes which can meet this challenging cost target and to proof that such a solar cell can be produced in large scale. Key priorities are focused on the development of a new growth reactor with efficient use of the precursor gases, enhanced waste treatment, recycling of metals and low cost preparation of the c-Si growth substrate. High performance devices will be demonstrated in an industrial relevant environment. The project SiTaSol approaches these challenges with a strong industrial perspective and brings together some of the most well-known European partners in the field of Si PV and III-V compound semiconductors. Furthermore SiTaSol will support the competitiveness of the European industry by providing innovative solutions for lowering manufacturing costs of III-V materials which are essential in today’s electronic products including laptops, photonic sensors and light emitting diodes.

Our modern society has gained enormously from novel miniaturized microelectronic products with enhanced functionality at ever decreasing cost. However, as size goes down, interconnects become major bottlenecks irrespective of the application domain. CONNECT proposes innovations in novel interconnect architectures to enable future CMOS scaling by integration of metal-doped or metal-filled Carbon Nanotube (CNT) composite. To achieve the above, CONNECT aspires to develop fabrication techniques and processes to sustain reliable CNTs for on-chip interconnects. Also challenges of transferring the process into the semiconductor industry and CMOS compatibility will be addressed. CONNECT will investigate ultra-fine CNT lines and metal-CNT composite material for addressing the most imminent high power consumption and electromigration issues of current state-of-the-art copper interconnects. Demonstrators will be developed to show significantly improved electrical resistivity (up to 10µOhmcm for individual doped CNT lines), ampacity (up to 108A/cm2 for CNT bundles), thermal and electromigration properties compared to state-of-the-art approaches with conventional copper interconnects. Additionally, CONNECT will develop novel CNT interconnect architectures to explore circuit- and architecture-level performance and energy efficiency. The technologies developed in this project are key for both performance and manufacturability of scaled microelectronics. It will allow increased power density and scaling density of CMOS or CMOS extension and will also be applicable to alternative computing schemes such as neuromorphic computing. The CONNECT consortium has strong links along the value chain from fundamental research to end‐users and brings together some of the best research groups in that field in Europe. The realisation of CONNECT will foster the recovery of market shares of the European electronic sector and prepare the industry for future developments of the electronic landscape