Efforts to develop optical interfaces with Terabit capacity for datacom applications have kicked off. A practical path to the Terabit regime is to scale the current 400G modules, which are based (in the most forward looking version of the standards) on 4 parallel lanes, each operating with PAM-4 at 53 Gbaud. Scaling these modules by adding lanes looks simple, but entails challenges with respect to the fabrication and assembly complexity that can critically affect their manufacturability and cost. TERIPHIC aims to address these challenges by leveraging photonic integration concepts and developing a seamless chain of component fabrication, assembly automation and module characterization processes as the basis for high-volume production lines of Terabit modules. TERIPHIC will bring together EML arrays in the O-band, PD arrays and a polymer chip that will act as the host platform for the integration of the arrays and the wavelength mux-demux of the lanes. The integration will rely on butt-end-coupling steps, which will be automated via the development of module specific alignment and attachment processes on commercial equipment. The optical subassembly will be mounted on the mainboard of the module together with linear driver and TIA arrays. The assembly process will be based on the standard methodologies of MLNX and the use of polymer FlexLines for the interconnection of the optical subassembly with the drivers and the TIAs. Using these methods, TERIPHIC will develop pluggable modules with 8 lanes (800G capacity) and mid-board modules with 16 lanes (1.6T capacity) having a reach of at least 2 km. Compared to the 400G standards, the modules will reduce by 50% the power consumption per Gb/s, and will have a cost of 0.3 Euro/Gb/s. After assembly, the modules will be mounted on the line cards of MLNX switches, and will be tested in real settings. A study for the consolidation of the methods and the set up of a pilot assembly line in the post-project era will be also made.

InP photonic integrated circuits (PICs) offer game changing performance capabilities across multiple market sectors. Alas, the possibilities have so far been restricted to a small number of vertically-integrated technology businesses. Europe boasts tens of innovative businesses who are positioned to develop PIC-enabled technologies , but – alas again – they do not have access to mature, fast-turnaround predictable, high performance production. InPulse is a manufacturing pilot line for InP PICs which will transform the PIC industry from a vertically integrated model with all skills in-house within a small number of specialized businesses, to an open-access horizontal model accessible to all European innovators. InPulse puts in place the technological and operational processes to: 1) Accelerate the uptake of PIC technology in new markets: enabling SMEs to create tens of products in markets where PICs have not be used before. 2) Enable sustainable production in Europe creating aligned, scalable and inter-locking services and value chains 3) Accelerate time to market from years to under 24 months with predictive design for fewer and faster product design cycles 4) Qualify foundry processes, to TRL7, sharing process optimization across products InPulse combines low entrance-threshold, mature-manufacturing to enable tens of European PIC innovators. InPulse is validated by: • A “Pilot Line Validation Program” with two Participants stretching performance • A “Demonstrator Open Call” program enabling external users to take thirty designs to pre-production • High frequency open access calls, sustainable beyond the end of the project InPulse partners have played a pioneering role in open access InP PICs, creating an infrastructure for research and early stage development. We are very well positioned to enable high TRL development in a scalable design kit driven process driving open access InP PICs from proof of concept to industrial prototyping and pre-production.

This proposal aims to develop the most competitive cameras for Face-Recognition, Mixed Reality and Augmented Reality for mobile phones, tablets and laptop computers. An embedded camera module, a highly competitive device aiming towards disruptive marketshare and global leaderhip. Our device reduces by more than 50% the costs of the BOM (Bill of Material) for the camera, increases drastically the resolution of the depth map (from 40 Kpixels to 1,45 Mpixels), provides real-time-video and consumes much lower power. Our commercial contacts with Korean, Chinese and Taiwanese manufacturers of mobile phones and tablet computers, customers for our first Depth-cameras, confirm that our disruptive 3D imaging devices will sell millions of units in the first year following initial design win(s). According to IDC and WCP, well-known analyst firms, the number of Smart Phones, tablets and laptops forecasted for 2018 will reach 2.25 billion devices. A large percentage of the manufacturers of this combined total of 2.25 billion consumer electronic products are potential customers for us. Our most disruptive competitive advantage is based on our algorithms (with only 1% of the computing power required by competition): we create high-quality depth-maps, 3D-content and all-in-focus images, we can process 60 fps videos under ANDROID processors while competitors need seconds to minutes to process a single frame with powerful GPUs. We disrupt into established value-chains accelerating the development of ideas into business-driven new products targetting to bring turnovers of € 2 billion by 2022-23 to the partners of this consortium. Synergies with existing products guarantee a swift exploitation of results starting before the end of the project.

Lasers are a ubiquitous technology in optical communication, sensors, LiDAR or emerging quantum science and technology. Yet, the principles by which lasers are manufactured have remarkably not changed since the invention of the laser: they are assembled by hand, using bulk components or optical fibers. While integrated lasers based on silicon photonics exist, they do not challenge such high performance legacy lasers systems. FORTE will change this notion. Building on a recent breakthrough in the field of low loss integrated photonics it is today possible to create lasers that are low cost, wafer scale manufacturable that have better performance that the fiber laser the workhorse of fiber sensing and gold standard in coherence. The overarching ambition of this EIC transition project is to develop a prototype and mature photonic integrated circuit-based frequency-agile ultra-low noise laser technology, and apply it to the domain of fiber sensing and FMCW LiDAR, and to develop a scalable manufacturing. The unique selling points (USP) of the platform are that it is based on photonic integrated circuit technology that is scalable, flexible, reconfigurable, and extremely high performance in terms of optical coherence and frequency-agility. The technology is based on a patented approach that combines ultra-low loss photonic integrated circuits based on silicon nitride, with MEMS technology, as used in wireless technology. The approach addresses the need for low-noise laser sources in multiple domains of photonic sensing including distributed fiber optic sensing (DFOS) and coherent laser ranging (FMCW LiDAR). The consortium includes companies in fiber sensing, LiDAR as well as in the development of industrial manufacturing tools. The results will be commercialized by the involvement of SME in fiber sensing, and a dedicated startup to bring hybrid integrated frequency agile low noise lasers to the market.

MASSTART aims to provide a holistic transformation to the assembly and characterization of high speed photonic transceivers towards bringing the cost down to €1/Gb/s or even lower in mass production. This will guarantee European leadership in the Photonics industry for the next decade. MASSTART will surpass the cost metric threshold by using enhanced and scalable techniques: i) glass interface based laser/PIC and fiber/PIC coupling approaches, leveraging glass waveguide technology to obtain spot size and pitch converters in order to dramatically increase optical I/O density, while facilitating automated assembly processes, ii) 3D packaging (TSV) enabling backside connection of the high speed PIC to a Si carrier iii) a new generation of flip chip bonders with enhanced placement in a complete assembly line compatible with Industry 4.0 which will guarantee an x6 improvement in throughput and iv) wafer-level evaluation of assembled circuits with novel tools that will reduce the characterization time by a factor of 10, down to 1 minute per device. This process flow will be assessed with the fabrication and characterization of four different demonstrators, addressing the mid-term requirements of next generation transceivers required by Data Center operators and covering both inter- and intra- Data Center applications. These demonstrators are: i) a 4-channel PSM4 module in QSFP-DD format with 400G aggregate bit rate, ii) an 8-channel WDM module in a QSFP-DD format with 800G aggregate bit rate, iii) a 16-channel WDM on-board module delivering 1.6Tb/s aggregate line rate and iv) a tunable single-wavelength coherent transceiver with 600Gb/s capacity following the DP-64QAM modulation format on 64Gbaud/s line rate. Finally, MASSTART will interact closely with international bodies to ensure the compliance and standardization of the developed technology with other proposed packaging form factors for rapid commercialization.