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THALES DIS FRANCE SAS

Country: France

THALES DIS FRANCE SAS

14 Projects, page 1 of 3
  • Funder: European Commission Project Code: 101167964
    Funder Contribution: 3,133,960 EUR

    PRIVIDEMA represents an industry-driven initiative to advance privacy-preserving technologies in the application areas of cyber threat intelligence, data protection, and identity management. This multifaceted project operates across various research and innovation maturity levels, with the overarching goal of introducing more robust, user-friendly and scalable privacy and security technologies for the European ecosystem. Key components of PRIVIDEMA include: 1. Development of open-source tools, hosting networking events, and initiation of capacity-building efforts to democratize technology access and empower cybersecurity professionals. 2. Advancement of homomorphic encryption capabilities, implementation of hardware acceleration methods, and improvement of Fully Homomorphic Encryption (FHE) usability. 3. Creation and demonstration of a prototype European identity wallet featuring issuer and relaying party functionalities. 4. Development and demonstration of a prototype European privacy-preserving cyber threat data processing system, with real-world testing and validation of innovative technologies. Aligned with the objectives of Horizon Europe, PRIVIDEMA actively contributes to increased cybersecurity, data and network protection, and the establishment of robust digital infrastructures. The project distinguishes itself through its commitment to supporting SMEs as well as promoting open-source development, cross-disciplinary collaboration, and privacy-by-design principles. The solution-oriented approach positions PRIVIDEMA as a pivotal force in advancing cyber-resilient digitalization and the data economy in Europe. PRIVIDEMA's connection to various European strategic initiatives underscores its relevance, with a clear emphasis on real-world applications, innovation beyond the state-of-the-art, and a strategic trajectory toward market-ready solutions.

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  • Funder: European Commission Project Code: 101112274
    Overall Budget: 39,410,100 EURFunder Contribution: 11,582,700 EUR

    The ISOLDE project aims to significantly support the digital transformation of all economic and societal sectors, to speed up the transition towards a green, climate neutral and digital Europe, to strengthen the design capacity and to achieving digital autonomy EU wide. By the end of our project, we will have high performance RISC-V processing systems and platforms at least at TRL 7 for the vast majority of building blocks, demonstrated for key European application domains such as automotive, space and IoT with the expectation that two years after completion ISOLDE’s high performance components will be used in industrial quality products. To achieve such an ambitious goal, an industrial-grade open-source support for development, verification, and maintenance will be provided. The customizable IPs will be hosted on physically located European servers to address the European digital sovereignty requirement that the ISOLDE project will support. This way, ISOLDE will have delivered a major contribution to the unification and focus of the full-fledged – industry-supported – eco-system for RISC-V open-source architecture, especially in the area of embedded high-performance computing, and thus to the creation of a breakthrough design capacity across the EU microelectronics industry.

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  • Funder: European Commission Project Code: 952622
    Overall Budget: 5,041,090 EURFunder Contribution: 5,041,090 EUR

    Our society is continuously demanding more and more intelligent devices, along with network infrastructures and distributed services that make our daily lives more comfortably. However, the frantic adoption of Internet of Things (IoT) technologies has led to widespread implementations without a deep analysis about security matters. This project encompasses the complete design of a platform, so-called SPIRS platform, which integrates a hardware dedicated Root of Trust (RoT) and a processor core with the capability of offering a full suite of security services. Furthermore, the SPIRS platform will be able to leverage this capability to support privacy-respectful attestation mechanisms and enable trusted communication channels across 5G infrastructures. RoT is implemented in hardware with a dedicated circuitry to extract a unique digital identifier for the SPIRS platform during its entire lifetime. To build a complete solution, the project also features a Trusted Execution Environment (TEE), secure boot, and runtime integrity. Furthermore, resilience and privacy protection are major concerns in this project, and it endeavors to the design of a decentralized trust management framework targeted to minimize the impact of Single Point of Failure (SPOF) risks and achieve adequate security and privacy tradeoffs. To facilitate the tasks of validation and testing, SPIRS platform is conceived as an open platform that can easily integrate other building blocks and facilities upgrades. The project goes beyond the construction of the SPIRS platform and it provides solutions to integrate it in the deployment of cryptographic protocols and network infrastructures in a trustworthy way, leveraging the RoT provided by the platform. To validate SPIRS results, the project considers two different scenarios: Industry 4.0 and 5G Technologies.

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  • Funder: European Commission Project Code: 101096456
    Overall Budget: 6,447,430 EURFunder Contribution: 5,999,800 EUR

    The overall aim of NANCY is to introduce a secure and intelligent architecture for the beyond the fifth generation (B5G) wireless network. Leveraging AI and blockchain, NANCY enables secure and intelligent resource management, flexible networking, and orchestration. In this direction, novel architectures, namely point-to-point (P2P) connectivity for device-to-device connectivity, mesh networking, and relay-based communications, as well as protocols for medium access, mobility management, and resource allocation will be designed. These architectures and protocols will make the most by jointly optimizing the midhaul, and fronthaul. This is expected to enable truly distributed intelligence and transform the network to a low-power computer. Likewise, by following a holistic optimization approach and leveraging the developments in blockchain, NANCY aims at supporting E2E personalized, multi-tenant and perpetual protection.

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  • Funder: European Commission Project Code: 101007321
    Overall Budget: 99,414,800 EURFunder Contribution: 24,932,300 EUR

    The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt. The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the support technology to demonstrate the high performances path as well as the robustness of the ePCM solution. The next generation of FDSOI ePCM will be main path for general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security. On top of the development and industrialization of silicon process lines and SoC design, storAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.

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