SESAME targets innovations around three central elements in 5G: the placement of network intelligence and applications in the network edge through Network Functions Virtualisation (NFV) and Edge Cloud Computing; the substantial evolution of the Small Cell concept, already mainstream in 4G but expected to deliver its full potential in the challenging high dense 5G scenarios; and the consolidation of multi-tenancy in communications infrastructures, allowing several operators/service providers to engage in new sharing models of both access capacity and edge computing capabilities. SESAME proposes the Cloud-Enabled Small Cell (CESC) concept, a new multi-operator enabled Small Cell that integrates a virtualised execution platform (i.e., the Light DC) for deploying Virtual Network Functions (NVFs), supporting powerful self-x management and executing novel applications and services inside the access network infrastructure. The Light DC will feature low-power processors and hardware accelerators for time critical operations and will build a high manageable clustered edge computing infrastructure. This approach will allow new stakeholders to dynamically enter the value chain by acting as 'host-neutral' providers in high traffic areas where densification of multiple networks is not practical. The optimal management of a CESC deployment is a key challenge of SESAME, for which new orchestration, NFV management, virtualisation of management views per tenant, self-x features and radio access management techniques will be developed. After designing, specifying and developing the architecture and all the involved CESC modules, SESAME will culminate with a prototype with all functionalities for proving the concept in relevant use cases. Besides, CESC will be formulated consistently and synergistically with other 5G-PPP components through coordination with the corresponding projects.

The fundamental goal of the ANDANTE project is to leverage innovative hardware platforms to build strong hardware / software platforms for artificial neural networks (ANN) and spiking neural networks (SNN) as a basis for future products in the Edge IoT domain, combining extreme power efficiency with robust neuromorphic computing capabilities and demonstrate them in key application areas. The main objective of ANDANTE is to build and expand the European eco-system around the definition, development, production and application of neuromorphic hardware through an efficient cross-fertilization between major European foundries, chip design, system houses, application companies and research partners, as presented by the European Leader Group (ELG). The project brings together world class expertise to bring the world class expertise and infrastructures of Imec, CEA and FhG together with semiconductor companies, fabless, system houses, SMEs and application experts to explore and demonstrate the capabilities provided by the developed technologies. In the project, several applications will be assessed in key domains where Europe is strong (automotive, digital farming, digital industry, mobility and digital life). The aim is to reinforce and maintain strong leadership in these areas by bringing industry in contact with future memory technologies at a low TRL level (MRAM, OXRAM, FeFET). These cross-disciplinary efforts will lead to development of innovative hardware / software deep learning solutions, based on high TRL level RRAM/PCM and FeFET, to enable future products which combine extreme power efficiency with robust cognitive computing capabilities. This new kind of computing technology, combining ANN and SNN capabilities, will open new perspectives, for instance, environmental monitoring, and wearable electronics.

The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform. Additional developments will be performed for the integration of memory, power management, connectivity, hard security on the same chip. The project will also target the industrialization of the embedded Phase Change Memory (PCM) technology built on top of the FDSOI 28nm logic process pilot line. The development of the ePCM will be driven by the final application requirements as well as decreasing the power consumption. The alternative memory solutions will be also studied as they have different - and complementary - traits in such areas as read/write speed, power and energy consumption, retention and endurance, and device density and benchmarked with the ePCM and the conventional eFlash. Continued advances in materials, device physics, architectures and design could further reduce the energy consumption of these memories. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage. These activities encompass such developments as: technology enhancements for various specific application requirements such as wide temperature range and reliability, high security requests, high flexibility…, design enablment allowing first time silicon success, prototyping demonstrator products in the different application areas. In the WAKEMEUP project, new devices and systems will be developed by the application partners in automotive and secure based on FD-SOI and embedded digital technology to answer specific applications needs.

The 2DTherm project tackles the ability to use Raman spectroscopy of two-dimensional materials to act as absolute nanoscale temperature probes for the development of power electronics on SiC and GaN. Indeed, current densities are such that local temperature can reach up to 350°C under certain operational conditions in these devices. Probing the local temperature is thus a crucial element as it impacts their lifetimes, degradation mechanisms and device performances. However, conventional approach by thermal simulation and infrared mapping is not sufficient as it only measures the temperature gradients. Here we propose that by using 2D materials on the device surface, very precise absolute temperatures measurements should be made possible thanks to the Raman technique (using the ratio of Stokes/Antistokes peaks or the Stokes peaks position). As a proof of concept our technique will be applied to the latest generation of power devices from STMicroelectronics. To do this, the consortium will explore the most interesting 2D materials in terms of deposition (PLD, CVD..), transfer on transistor (local buffer, pick and place, spray), Raman signature and electrical and thermal properties, and this on real bare chips and transistors in de-encapsulated plastic case. The local absolute temperature measurements will eventually allow to correct the thermal simulations, to refine the electrothermal models of the transistors to ensure the performance of the systems in a concern of reliability with cost and energy saving (dimensioning of the cooling systems) for greener electronics.

EdgeAI is as a key initiative for the European digital transition towards intelligent processing solutions at the edge. EdgeAI will develop new electronic components and systems, processing architectures, connectivity, software, algorithms, and middleware through the combination of microelectronics, AI, embedded systems, and edge computing. EdgeAI will ensure that Europe has the necessary tools, skills, and technologies to enable edge AI as a viable alternative deployment option to legacy centralised solutions, unlocking the potential of ubiquitous AI deployment, with the long-term objective of Europe taking the lead of Intelligent Edge. EdgeAI will contribute to the Green Deal twin transition with a systemic, cross-sectoral approach, and will deliver enhanced AI-based electronic components and systems, edge processing platforms, AI frameworks and middleware. It will develop methodologies to ease, advance and tailor the design of edge AI technologies by co-ordinating efforts across 48 of the brightest and best R&D organizations across Europe. It will demonstrate the applicability of the developed approaches across a variety of vertical solutions, considering security, trust, and energy efficiency demands inherent in each of these use cases. EdgeAI will significantly contribute to the grand societal challenge to increase the intelligent processing capabilities at the edge.