For future ICT industry, the elephant in the room is Internet of Things (IoT) and Artificial Intelligence (AI). They are driving the fourth industrial revolution that is profoundly changing how we live and interact. The main issues for IoT and AI have been identified as: power, security, and cost. This project is co-created with the industrial partners and focuses on the power issue. One of the most effective way for reducing power is by lowering the operation voltage, Vg, towards the transistor threshold voltage, Vth. This has motivated recently extensive research in near threshold voltage computing. As Vg approaches Vth, the operation window (Vg-Vth) reduces and the system will be increasingly vulnerable to instability in Vth: a small rise in Vth can effectively switch off a transistor. Instability causes faults in operation, such as read and write errors in SRAM and digital timing errors. It is a limiting factor for how low (Vg-Vth) and, in turn, how much power consumption can be reduced. One of the critical tasks for low power system optimization is to minimise operation voltage and power consumption that will deliver specified yield 'Y' in 'X' years at a temperature below 'T'. To complete this optimization, designers need a fault analysis model that gives the time evolution of the probability distribution of Vth and driving current, Id, at a given distance from their target values. The further Vth and Id depart from their target values, the more likely a circuit will fail. Despite of decades of research, a reliable fault model is still not available. Indeed, in a recent review, the lack of realistic fault model tops the list of challenges for Cognitive Computing System design. Although the need for this model is clear, even world-leading EDA suppliers and foundries cannot deliver the model and current SPICE models simply do not include Jitter. This is related to weaknesses of previous research, including statistically inconsistent bottom-up methodology, limited time window, weak model verification criterion, and the neglect of the interaction of different instability sources. The fabless UK IC-design companies are using foundries for their chip fabrication. Software is the essential bridge between designers and foundries. As there are no generally accepted realistic fault models at present, designers have to rely on adding a guard-band (design margins) obtained from empirical 'worst case guess'. This contributes to the substantial discrepancy between design and Si performance. As CMOS nodes are downscaled to nano-meter range, the stochastic spreading of device parameters increases dramatically this discrepancy, which has been identified as a major challenge for optimizing the design of low power IoT and Cognitive Computing Systems. The aim of this project is to provide the world first test-proven fault model that enables statistical, dynamic, and quantitative analysis of fault rate and in turn the optimization of low power IoT and Cognitive Computing Systems. Novel techniques and methodologies will be employed to overcome the weakness of early works, including a top-down approach to remove device selection, advanced data acquisition method for long time window, qualifying the model by prediction capability, covering the interactions between different sources of instabilities. The developed model will be tested against Si performance of real circuits together with the industrial project partners. If successful, it will deliver a paradigm shift from one-size-fit-all to application specific fault analysis and optimization, reducing power and time-to-market.

Supercomputers (HPC) provides exciting opportunities for simulation-led design of materials and processes. Our project builds on the expertise in the UK Materials Chemistry Consortium, to exploit world-leading supercomputers with a programme of research into the behaviour of the materials used in applications and devices including thin-film solar cells, high-capacity batteries, flexible electronic displays, hosts for toxic waste products, biomaterials with medical applications, and cheaper and more efficient production of green fuels and of bulk and fine chemicals from detergents to medicines, thus transforming society and people's lives. The project comprises application-driven and cross-cutting themes focused on fundamental challenges in contemporary materials chemistry and physics and advanced methodology. It brings together the UK's materials academic community, currently representing 38 universities. Close interaction will promote rapid progress, novel solutions, and best practice resulting in both applied and fundamental developments. Our work will be guided by an advisory panel of leading international academics and industrial experts and collaborators. Our goal is to maintain a vigorous scientific endeavour within the current membership and in doing so attract likeminded professionals and non-traditional HPC users. Tuning properties of materials forms the backbone of research in Energy Conversion, Storage and Transport, a key application theme for the UK's economy and net-zero targets. We will aim to improve the performance of materials used in both batteries and fuel cells, as well as novel types of solar cells. In Reactivity and Catalysis, we will develop realistic models of several key catalytic systems. Targets relate strongly to the circular economy and include CO2 activation and utilisation, green ammonia production, biomass conversion and enhancement of efficiency in industrial processes and more effective reduction in air pollution. We will develop environment protecting materials to contain toxic and/or radioactive waste, capture greenhouse gases for long-term storage, remove toxins and pollutants from the biosphere to improve wildlife and human health, and control transmission of solar energy through windows. Work on Biomaterials will reveal the fundamental processes of biomineralisation, which drives bone repair and bone grafting, with a focus on synthetic bone replacement materials. Materials Discovery will support screening materials using global-optimisation-based approaches to develop tailored chemical dopants, improving the desired property of a device, and searching the phase diagram for solid phases of a pharmaceutical drug molecule. Crosscutting themes will focus on basic issues in the physics and chemistry of matter that underlie the application themes. They will address: challenges in predicting the morphology, atomic structure and stability of different phases; defects and their role in material growth, corrosion and dissolution in Bulk, Surfaces and Interfaces, and at Nano- and meso-scales. Our simulations will investigate materials far from equilibrium, as well as quantum and nano-materials with links to topological spintronics. Software developments will include utilising machine learnt potentials, significantly increasing the time- and length-scales of simulations (compared to electronic structure-based calculations) without compromising their accuracy and predictive power. We will continue to develop new functionalities and optimise performance of internationally leading materials software and link to research exploiting quantum computers. We will continue training postgraduate students and researchers in the use of HPC resources and application of scientific software to materials problems. As experts, we will continue to perform the crucial knowledge transfer providing expertise to the UK society from the school level up to the Government funding agencies.

Please see main (Glasgow) form

The years of 'happy scaling' are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems. This proposal brings together semiconductor device, circuit and system experts from academia and industry and e-scientists with strong grid expertise. Only by working in close collaboration, and adequately connected and resourced by e-science and Grid technology, can we understand and tackle the design complexity of nano-CMOS electronics, securing a competitive advantage for the UK electronics industry.Increasing variability in device characteristics and the need to introduce novel device architectures represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers. This can only be achieved by embedding e-science technology and know-how across the whole nano-CMOS electronics design process and revolutionising the way in which these disparate groups currently work.This project's over-arching aim is to revolutionise existing nano-CMOS electronics research processes by developing the methodology and prototype technology of a nano-CMOS Design Grid. We use the term Grid to encompass computing technologies that allow distributed groups to collaborate by sharing designs, simulations, workflows, data sets and computation resources. This work will require a deep understanding of how electronics scientists, engineers and designers can work together to produce new methods and results. Through this process we will create Grid-savvy nano-CMOS e-Researchers able to Grid-enable their own simulations, to correctly annotate their own data, to design workflows reflecting their design processes, and share all these with other researchers in the nano-CMOS design space.

See Joint Proposal E241901