The semiconductor industry has provided the devices we have enjoyed for many years, including mobile phones, personal computers, on-line banking etc. The growing functionality of these products is a result of making the components, namely transistors and memory elements, ever smaller, at the rate that in every 18 months or so the number of components in a given area has doubled, which also makes the devices run faster. The industry now runs into a fundamental roadblock in shrinking the devices further, so we need to look for a new device type which will continue to provide higher performance. One strong contender is the RRAM (resistive random access memory) which we will investigate in this project. This device can be programmed to offer either a high or low electrical resistance: that is, store a logic "0" or "1", or even with some intermediate levels in between. It can store information which will remain even after the power is turned off, as so called non-volatile. With this device, a number of disruptive developments are under intensive research world-wide. Its first potential application is to increase the speed of the non-volatile memory chip in computers by more than 10 times and provide potential for further increase in the number of components. The second is in the artificial intelligence (AI) computing which mimics the functionality of human brains. AI has been widely used by Google, Facebook, Apple, etc. RRAM has the potential to bring a breakthrough in AI by solving the density, connectivity and memory bandwidth limitations of AI hardware based on conventional devices. The third is to revolutionise the programmable computing with its smaller size and non-volatility, providing advantages for computing in data centres and Internet of Things, in which the vast amount of data will be streamed through internet and the scalability and energy efficiency provided by RRAM become critical. The behaviour of RRAM devices, however, is stochastic, meaning that a large variation occurs during the device operation. At present, the lack of systematic understanding of the variability and the missing tools for variability-aware simulation hinder the research progress in RRAM-based circuit and systems design for neuromorphic and programmable computing. In this project we will collaborate with UK's leading IC design company, ARM Holdings, and the world no.1 EDA software company, Synopsys, providing direct insight into the fundamental properties of RRAM variability and developing a predictive variability-aware product design kit (PDK) that can be directly used within commercial EDA software by designers, enabling the research and design of novel RRAM based neuromorphic and programmable computing systems. We expect this project to have a significant direct impact on the UK and global ICT industry in the forthcoming Artificial Intelligence (AI) and Internet of Things (IoT) era.

Flash memories are used to store phone numbers, music, pictures and videos in mobile phones and are also frequently now used in place of magnetic hard disks in laptop computers. Such memories are non-volatile retaining information even if a battery looses all charge. Consumers constantly want more memory on their portable electronic devices to allow more video and music to be stored but flash memory is already close to the scaling limits preventing significant increases to memory sizes in the future. A flash memory consists of a floating gate charge node where the a single bit of digital information is stored as a "1" when the node is charged and "0" when the node is discharged. As the floating gate is reduced in size, there are more errors when electrons leak out of or onto the floating gate. These errors result from variation in floating gate size by just a few atomic layers which are sufficient to substantially change the applied voltage required to tunnel electrons onto or off the floating gate. This limit has been reached with present production. Our approach to improve flash memory and allow smaller memories is to use molecules which are produced chemically to allow charges to be stored as the digital memory and as the molecules are all identical, they do not suffer the same variability errors as the present silicon floating gate flash memories. Out ultimate aim is to use single molecules to enable further scaling thereby aiming to increase the amount of memory available in the future. We will also investigate molecules that can store more than "0" and "1" known as multi-valued memory. This multi-valued memory approach allows more bits to be stored on a single floating gate thereby allowing higher memory density expanding further what could be stored on a mobile phone or laptop computer. The approach we are taking requires the ability to measure the state an electron occupies on a single molecule. Therefore the technique developed here could be used to measure the properties of single molecules. This has potential applications for measuring the electronic properties of single molecules directly allowing the full characterisation of the molecular levels which at present is difficult to achieve. We believe these techniques can benefit a wide range of researchers in chemistry, physics, materials science and engineering in achieving far cheaper characterisation of materials at the nanoscale.

Semiconductor manufacturing test is affected by fabrication process and power supply voltage (PV) variation as demonstrated recently by the investigating team. Performing test using existing methods and without considering PV varaition will lead to defects being missed by during test leading to reduced yield and reliability of integrated circuits. This grant application is focused on exploring and developing new and efficient test methods capable of mitigating the impact of PV variation leading to improved test quality and higher dependability. This project will provide significant advances in the present state-of-the-art semiconductor test and will help to establish the scientific foundation required for the development of next generation PV variation-aware test methods and tools for nanoscale integrated circuits. This includes new fault models for resistive open and resistive short defects that capture PV variation; accurate metrics for assessing and quantifying the impact of such variation on the quality and cost of test, and two variation-aware test pattern generation methods (logic and delay) capable of mitigating test escapes due to PV variation and efficient in terms of defect coverage and volume of test data. The developed models, metrics, and test generation methods will be evaluated using comprehensive simulation with nano-meter synthesized benchmark circuits and real-life test problem provided by the project industrial partner. This is a three-year project involving one named post doctoral researcher and one PhD student. The project will be carried out in collaboration with ARM (Cambridge) and Synopsys (US), and in collaboration with Prof. K. Chakrabarty (Duke Uni.), and Prof. S. Kundu (Uni. of Massachusetts) as visiting researchers.The research we propose is aligned with the EPSRC signposted Grand Challenges in microelectronics design as identified by the EPSRC network grant Developing a Common Vision for UK Research in Microelectronic Design . This proposal is aligned in particular with GC3 (More for Less: Performance-driven design for next generation chip technology), where one of the main technical issues that need to be addressed in this GC is Test and Verification if the semiconductor industry is to continue to produce more efficient designs with better performance, lower power and lower test and verification cost.

For future ICT industry, the elephant in the room is Internet of Things (IoT) and Artificial Intelligence (AI). They are driving the fourth industrial revolution that is profoundly changing how we live and interact. The main issues for IoT and AI have been identified as: power, security, and cost. This project is co-created with the industrial partners and focuses on the power issue. One of the most effective way for reducing power is by lowering the operation voltage, Vg, towards the transistor threshold voltage, Vth. This has motivated recently extensive research in near threshold voltage computing. As Vg approaches Vth, the operation window (Vg-Vth) reduces and the system will be increasingly vulnerable to instability in Vth: a small rise in Vth can effectively switch off a transistor. Instability causes faults in operation, such as read and write errors in SRAM and digital timing errors. It is a limiting factor for how low (Vg-Vth) and, in turn, how much power consumption can be reduced. One of the critical tasks for low power system optimization is to minimise operation voltage and power consumption that will deliver specified yield 'Y' in 'X' years at a temperature below 'T'. To complete this optimization, designers need a fault analysis model that gives the time evolution of the probability distribution of Vth and driving current, Id, at a given distance from their target values. The further Vth and Id depart from their target values, the more likely a circuit will fail. Despite of decades of research, a reliable fault model is still not available. Indeed, in a recent review, the lack of realistic fault model tops the list of challenges for Cognitive Computing System design. Although the need for this model is clear, even world-leading EDA suppliers and foundries cannot deliver the model and current SPICE models simply do not include Jitter. This is related to weaknesses of previous research, including statistically inconsistent bottom-up methodology, limited time window, weak model verification criterion, and the neglect of the interaction of different instability sources. The fabless UK IC-design companies are using foundries for their chip fabrication. Software is the essential bridge between designers and foundries. As there are no generally accepted realistic fault models at present, designers have to rely on adding a guard-band (design margins) obtained from empirical 'worst case guess'. This contributes to the substantial discrepancy between design and Si performance. As CMOS nodes are downscaled to nano-meter range, the stochastic spreading of device parameters increases dramatically this discrepancy, which has been identified as a major challenge for optimizing the design of low power IoT and Cognitive Computing Systems. The aim of this project is to provide the world first test-proven fault model that enables statistical, dynamic, and quantitative analysis of fault rate and in turn the optimization of low power IoT and Cognitive Computing Systems. Novel techniques and methodologies will be employed to overcome the weakness of early works, including a top-down approach to remove device selection, advanced data acquisition method for long time window, qualifying the model by prediction capability, covering the interactions between different sources of instabilities. The developed model will be tested against Si performance of real circuits together with the industrial project partners. If successful, it will deliver a paradigm shift from one-size-fit-all to application specific fault analysis and optimization, reducing power and time-to-market.

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