The ISOLDE project aims to significantly support the digital transformation of all economic and societal sectors, to speed up the transition towards a green, climate neutral and digital Europe, to strengthen the design capacity and to achieving digital autonomy EU wide. By the end of our project, we will have high performance RISC-V processing systems and platforms at least at TRL 7 for the vast majority of building blocks, demonstrated for key European application domains such as automotive, space and IoT with the expectation that two years after completion ISOLDE’s high performance components will be used in industrial quality products. To achieve such an ambitious goal, an industrial-grade open-source support for development, verification, and maintenance will be provided. The customizable IPs will be hosted on physically located European servers to address the European digital sovereignty requirement that the ISOLDE project will support. This way, ISOLDE will have delivered a major contribution to the unification and focus of the full-fledged – industry-supported – eco-system for RISC-V open-source architecture, especially in the area of embedded high-performance computing, and thus to the creation of a breakthrough design capacity across the EU microelectronics industry.

TRISTAN’S overarching aim is to expand, mature and industrialize the European RISC-V ecosystem so that it is able to compete with existing commercial alternatives. This will be achieved by leveraging the Open-Source community to gain in productivity and quality. This goal will be achieved by defining a European strategy for RISC-V based designs including the creation of a repository of industrial quality building blocks to be used for SoC designs in different application domains (e.g. automotive, industrial, etc.). The TRISTAN approach is holistic, covering both electronic design automation tools (EDA) and the full software stack. The broad consortium will expose a large number of engineers to RISC-V technology, which will further encourage adoption. This ecosystem will ensure a European sovereign alternative to existing industrial players. The 3-year project fits in the strategy of the European Commission to support the digital transformation of all economic and societal sectors, and speed up the transition towards a green, climate neutral and digital Europe. This transformation includes the development of new semiconductor components, such as processors, as these are considered of key importance in retaining technological and digital sovereignty and build on significant prior investments in knowledge generation in this domain. Development strategies leveraging public research funding that exploit Open-Source have been shown to boost productivity, increase security, increase transparency, allow better interoperability, reduce cost to companies and consumers, and avoid vendor lock-ins. The TRISTAN consortium is composed of 46 partners from industry (both large industries as well as SMEs), research organizations, universities and RISC-V related industry associations, originating from Austria, Belgium, Finland, France, Germany, Israel, Italy, the Netherlands, Poland, Romania, Turkey and Switzerland.

Data and AI-driven smart technologies, with an emphasis on (i) the connection between the urban space and the industrial space, (ii) sustainable living and (ii) sustainable industrial production, hold the transformative potential to enhance the sustainability and climate resilience across EU, in private and work spaces. Assuming this, NexTArc is devoted to augmenting the adoption of Trustworthy edge AI and IoT across 3 complementary and interrelated application domains, organised as Use Cases (UC): SLN - Smart, sustainable and Liveable Neighbourhood in Urban Spaces; STI - Smart, sustainable and transparent industrial Spaces; and TEM - Trustworthy and Eco-friendly Multimodal Connectivity of Urban and Industrial Spaces through people and freight mobility, incl. the inter and intra-mobility. Building on this vision, NexTArc aims to promote the cross-fertilization of ideas among a broad spectrum of stakeholders, 38 partners in 10 countries, integrated over a four-fold Innovation Module (IM) approach: i) cyber-resilience on chip; ii) low-power embedded AI; iii) improved computation and dependability covering the high-performance needs; iv) holistic solution stack to enable trustworthy services, which resonate with the EU Chips Act, etc. NexTArc has identified 6 Specific Objectives: 1) Driving adoption of AI while enhancing connectivity preparedness; 2) Targeting a 40% increase in data transmission rates and a 30% reduction in energy use during data processes, while ensuring robust architectural resilience; 3) Fortifying cyber-physical security with an aim for full-compliance with EU’s Chip and Cybersecurity act; 4) Realising open HW/SW to ensure designs that are secure, safe, private, and accountable; 5) Proactively adapting to the dynamic landscape of open-source innovations and key industry standards; 6) Orchestrating 4 IM, unveiling 15 Key Innovations to develop the solutions that are needed for Europe to take the technological lead towards a sustainable society.

The project OPEVA aims for innovation on aggregating information from the vehicle, not only from the battery but also from other internal sensors and behaviours, to create a model of performance and consumption specific to the individual vehicle and its driver (TD1). It aims to optimize the individual driving episode using the out-vehicle data such as state of the road, weather, charging station location and occupancy etc. that are collated from the back-end systems (TD2). OPEVA will further address the challenges associated with the communication between the vehicle and the infrastructure to gather data from the back-end systems (TD3). It aims for innovation in the use of recharging stations and related applications (TD4). It further aims to achieve better understanding on what the battery and its constituent cells are really doing during real world use for an improved battery management system (TD5). Finally, TD6 covers the driver-oriented human factors for optimizing the electrical vehicle usage. The TDs from the most deeply embedded in the vehicle to its support in the cloud, which need to interwork in an optimal fashion to deliver in one decade a better level of systemic optimisation for personal mobility that took ten decades to achieve with fossil fuels. On the other hand, economic factors (N-TD1), legal and ethical aspects (N-TD2), EV related development by the human (N-TD3), and societal and environmental factors (N-TD4) will be taken into consideration in the OPEVA methods for a higher acceptance and the awareness of the society regarding the these developments.

Electrification and autonomy drive the rapid evolution of modern vehicles, requiring increasing computational capabilities, coupled with safety and efficiency. The classical, decentralized multi- Electronic Control Units (ECU) architecture has significant drawbacks when it comes to scalability, and it is becoming untenable. The dominant megatrend pushes for an increasing number of key functionalities to be software-defined, with the direct implication that the software content (lines-of-code) in a vehicle will grow by 10x in just 5 years, to 1 billion by 2030. From a hardware viewpoint, increased complexity and autonomy requires a more centralized approach to on-board computing to curtail cost, latency and bandwidth bottlenecks of the in-vehicle network. Centralizing the E/E architecture requires merging multiple Electronic Control Units (ECUs) into powerful, fully programmable Domain Control Units (DCUs) or Zonal Control Units (ZCUs). To address this paradigm shift, the Rigoletto project will establish the foundation for a next-generation Automotive Hardware Platform based on the open RISC-V instruction set architecture (ISA), bolstering and securing Europe's leading role in the automotive electronics industry. The project aligns with the high-level goal of EU Chips Joint Undertaking and the of the industry-led Vehicle of the Future initiative: namely, the creation of a RISC-V based automotive hardware platform strongly linked with the formation of an open, software-defined vehicle ecosystem led by European automotive manufacturers and suppliers. Rigoletto aims at developing RISC-V intellectual property (IP) components, including processor cores, accelerators, interconnects, memory hierarchy and peripheral subsystems. A wide range of performance profiles will be targeted for next-generation DCUs and ZCUs, to enable increasingly electrified, automated, and connected vehicles.