GENESIS, backed by Horizon Europe, aims to make semiconductor manufacturing sustainable, aligning with the European Green Deal, by minimizing environmental impact with eco-friendly innovations. [Objectives] GENESIS aims to replace harmful materials with safer options, improve waste management, and enhance the use and recyclability of scarce materials. [Innovations] GENESIS introduces innovations in three key areas: • Innovative materials: PFAS-free polymer and eco-friendly gas alternatives complying with EU regulations. • Waste & emissions monitoring: Cutting-edge sensors detect hazardous substances for efficient aqueous and gas waste elimination, reducing environmental and health risks. • Scarce material management: New integration technologies optimize material usage and initiate recycling of scarce materials like Gallium, Niobium, and silicon carbide. [Methodology] GENESIS employs four technical work packages to research sustainable material substitution, emission reduction, and resource management. This modular approach promotes scalability and integration with existing processes, fostering a circular economy in the semiconductor sector. Supervised by management work packages, it quantifies environmental efficiency and engages in dissemination to promote European technological achievements [Outcomes] The project targets a 50% cut in hazardous materials, 30% decrease in emissions and waste, and improved scarce material recyclability, boosting EU semiconductor sustainability and global competitiveness. [Impact] GENESIS supports EU's tech sovereignty and resilience through accurate monitoring and sustainable practices. It positions Europe as a leader in sustainable semiconductor tech, setting new standards for impact-oriented communication and dissemination.

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.

The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.