The performance of programming language implementations until 10 years ago relied on increasing clock frequencies on uni-core CPUs. The last decade has seen the rise of the multi-core era adding processing elements to CPUs, to enable general purpose parallel computing. Due to a single connection from multiple cores on a CPU to main memory, general purpose languages with parallelism support are finding the limits of general purpose CPU architectures that have been extended with parallelism. The fabric on which we compute has changed fundamentally. Driven by the needs of AI, Big Data and energy efficiency, industry is moving away from general purpose CPUs to efficient special purpose hardware e.g. Google's Tensorflow Processing Unit (TPU) in 2016, Huawei's Neural Processing Unit (NPU) in smartphones, and Graphcore's Intelligent Processing Unit (IPU) in 2017. This reflects a wider shift to special purpose hardware to improve execution efficiency. Functional languages are gaining widespread use in industry due to reduced development time, better maintainability, code correctness with assistance of static type checkers, and ease of deterministic parallelism. Functional language implementations overwhelmingly target general purpose CPUs, and hence have limited control over cache behaviour, sharing, prefetching and garbage collection locality. As such, they are reaching their performance limits due to the trade-off between parallelism and memory contention. This project takes the view that rather than using compiler optimisations to squeeze small incremental performance improvements from CPUs, special purpose hardware on programmable FPGAs may instead be able to provide a step change improvement by moving these non-deterministic inefficiencies into hardware. Graph reduction is a functional execution model that offers intriguing opportunities for developing radically different processor architectures. Early ideas stem back to the 1980s, well before the age of advanced Field Programmable Gate Array (FPGA) technology of the last 5-10 years. We believe that a bespoke FPGA memory hierarchy for functional languages could minimise memory traffic, thus avoiding the costs of cache misses and memory access latencies that quickly become the bottleneck for medium and large sized functional programs. We believe that lowering key runtime system components (prefetching, garbage collection, parallelism) to hardware, with a domain specific instruction set for graph reduction, will significantly reduce runtimes. We aim to inspire the computer architecture community to extend this project by developing accurate cost models for functional languages that target special purpose functional language hardware. Our HAFLANG project will target the Xilinx Alveo U280 accelerator board, a state-of-the-art UltraScale+ FPGA-based platform as a research vehicle for developing the FPU. The HAFLANG compilation framework will be designed to be extensible, and hence make the FPU processor a target for other languages in future. By developing a hardware accelerator, we believe it is possible to engineer a processor that (1) will execute programs with twice the throughput compared with GHC compiled Haskell executing on conventional mid-tier 4-16 core x86/x86-64 CPUs, and (2) consumes four times less energy than by executing programming languages on CPUs.

Energy efficiency is one of the primary design constraints for modern processing systems. Limited battery life and excessive internal power densities limit the number of transistors that can be active simultaneous in a silicon chip. Energy and power reduction in conventional computing is limited by the inability of modifying the architecture or adapting to changes in the fabrication process, temperature or application requirements after chip fabrication. When these changes are possible are limited by the need of "margining" that introduces safety margins so devices operate under worst conditions. Worst conditions are rarely the case an important energy and performance gains are possible if technology can adapt to the real conditions of operation. This research addresses this challenge by investigating energy proportional computing with a novel voltage, frequency and logic scaling triplet to adapt to changes in applications, fabrication or operating conditions. The results from this research are expected to deliver new fundamental insights to the question of: How future computers can obtain orders of magnitude higher performance with limited energy budgets?

Deep learning (DL) is the key technique in modern artificial intelligence (AI), which has provided state-of-the-art accuracy on many machine-learning based applications. Today, although most of the computational loads of DL systems are still spent running neural networks in data centres, the ubiquity of smartphones, and the upcoming availability of self-contained wearable devices for augmented reality (AR), virtual reality (VR) and autonomous robot systems are placing heavy demands on DL-inference hardware with high energy and computing efficiencies along with rapid development of DL techniques. Recently, we have witnessed a distinct evolution in the types of DL architecture, with more sophisticated network architectures proposed to improve edge AI inference. This includes dynamic network architectures that change with each new input in a data-dependent way, where inputs and internal states are not fixed. Such new architectural concepts in DL are likely to affect the type of hardware architectures that will be required to deliver such capabilities in the future. This project precisely addresses this challenge and proposes to design a flexible hardware architecture that enables adaptive support for a variety of DL algorithms on embedded devices. Primarily, to produce lower cost, lower power and higher processing efficiency DL-inference hardware that can be configured adaptably for dedicated application specifications and operating environments, this will require radical innovation in the optimisation of both the software and the hardware of current DL techniques. This work aims to perform fundamental research, development and practical demonstrator to enable general support for a variety of DL techniques on embedded edge devices with limited resource and latency budgets. Primarily, this requires radical innovation on the current DL architectures in terms of computing architecture, memory hierarchy and resource utilisation, as well as system latency and throughput: it is particularly important for the modern DL systems that the inference processes are dynamic, such as, the DL inference maybe input-dependent and resource-dependent. The proposal therefore seeks the following three thrusts: First, to build upon the existing work of the PI in optimising machine-learning models for resource-constrained embedded devices, towards achieving the goal that the network model could be dynamically optimised as needed through hardware-aware approximation techniques. Second, with newly-developed adaptive compute acceleration technology in programmable memory hierarchy and adaptive processing hardware, to seek a new ambitious direction to develop a set of context-aware hardware architectures to work closely with the approximation algorithms that can fully utilise the true hardware capabilities. Unlike traditional optimisation techniques for DL hardware inference engines, the proposed work will explore both software and hardware programmability of adaptive compute acceleration technology, in order to maximise the optimisation results for the target application scenarios. Third, this project will work closely with our industry and project partners to produce a practical demonstrator to showcase the effectiveness of the proposed DL framework versus traditional approaches, particularly, evaluating the effectiveness of the framework in real-world mission-critical applications.

The past years have witnessed a rapidly growing number of wirelessly-connected devices such as smartphones and Internet-of-Things (IoT) equipment, which generate ever-increasing amounts of data driving key Artificial Intelligence (AI) applications. However, users are increasingly unwilling to allow their private data (such as media, location, or sensor data) to be uploaded to a central location (e.g., cloud datacentre) for training Machine Learning (ML) models, and data-protection laws such as the Data Protection Act 2018 are growing more restrictive towards data usage. Federated Learning (FL) is a game-changing technology conceived to address the growing data privacy concern by moving training from the datacentre to user devices at the network edge, allowing sensitive data to remain on the devices where it was generated. FL has enormous potential for real-world, privacy-sensitive applications such as autonomous driving, diagnostic healthcare, and predictive maintenance. The operating environment for FL at the edge is extremely challenging for a variety of reasons: 1) the data owned by FL clients is highly heterogeneous (in regard to data distribution, quality, and quantity) and dynamic (data distributions change over time); 2) the hardware devices have diverse computing and communication capabilities with stringent resource constraints (e.g., battery power); and 3) FL clients work under unreliable wireless edge network conditions. Hence, despite FL's huge promise, there are considerable barriers to its wider real-world adoption for mission-critical AI applications that need real-time, on-demand responses, caused by several grand challenges: Challenge 1) lack of FL algorithms delivering consistent performance for dynamic client data, diverse client hardware, and unreliable wireless connections simultaneously; Challenge 2) lack of rigorous theoretical analyses of real-time, real-world FL algorithms; Challenge 3) lack of optimised, energy-efficient, versatile hardware acceleration for real-time FL. To address these important challenges, this project will create revolutionary algorithm-hardware co-design approaches to make FL a real-time process with unparalleled speed, performance, and energy-efficiency at the wireless edge, capable of meeting the stringent requirements of mission-critical applications. This research will pioneer a set of original methods and innovative technologies including: 1) disruptive lightweight hardware-aware FL algorithms that significantly reduce communication, computing, and energy costs while achieving fast model updates; 2) rigorous mathematical analyses of the proposed algorithms to prove their convergence rates and offer theoretical insights into how they perform under various edge network conditions; 3) an automatic hardware-software co-optimisation framework integrating specialised training-acceleration and power-reduction methods to realise optimised, energy-efficient hardware acceleration; and 4) a unique prototype system that will integrate the designed FL hardware accelerator and real-time FL algorithms and be evaluated in a realistic wireless edge networking testbed. This project has the potential to transform FL from a lengthy and disjointed process to a continuous, real-time procedure with concurrent model training and deployment. The proposed research will contribute to the UK's digital transformation and green economy by creating ground-breaking technologies for creating innovative AI-empowered products with significantly improved performance and energy-efficiency while complying with strict data-privacy protection.

There are increasing concerns about the safety and security of critical infrastructure such as nuclear power plants, the electricity grid and other utilities in the face of possible cyber attacks. As ageing controllers are replaced by smart devices based on Field-Programmable Gate Arrays (FPGAs) and embedded microprocessors, the safety of such devices raises many concerns. In particular, there is the very real risk of malicious functionality hidden in the silicon or in software binaries, dormant and waiting to be activated. Current hardware and software systems are of such complexity that it is impossible to discover such malicious code through testing. We aim to address this problem by closely connecting the system design specification with the actual implementation through the use of a formal design methodology based on type systems with static and dynamic type checking. The type system will be used as a formal language to encode the design specification so that the actual implementation will automatically be checked against the specification. Static type checking of data types and multiparty session types can ensure the correctness of the interaction between the components. However, as static checking assume full access to the design source code it cannot be used to protect against potential threads issuing from third-party functional blocks (know as ``Intellectual Property Cores'' or IP cores) that are commonly used in hardware design: the provider of the IP core can claim adherence to the types and protocols, so that the IP core will meet the compile-time requirements, but the run-time the behaviour cannot be controlled using static techniques. The same applies to third-party compiled software libraries. Therefore we propose to use run-time checking of data types as well as session types at the boundaries of untrusted modules ("Border Patrol"), so that any intentional or unintentional breach of the specification will safely be intercepted.