Quantum computation has just entered a new era, that of Noisy Intermediate-Scale Quantum (NISQ) technologies in which quantum processors are able to perform calculations beyond the capabilities of the world's greatest supercomputers. This remarkable achievement sets an important milestone in quantum computing (QC) and brings focus towards the ultimate goal of the QC roadmap: building a fault-tolerant quantum machine. A machine with sufficient error-free computing resources to run quantum algorithms with the potential to radically transform society. Algorithms that will help us better forecast weather and financial markets, speed up searches in unsorted databases, essential for the Big Data era, and most importantly, accelerate the pace of discovery of new materials and medicines, so relevant for the times we live in. The most promising routes to fault-tolerant QC will require quantum error correction (QEC) to enable accurate computing despite the intrinsically noisy nature of the individual quantum bits constituting the machine. The idea is based on distributing the logical information over a number of physical qubits. As long as the physical qubits satisfy a maximum error rate (1% for the most forgiving method, the surface code) fault-tolerance can be achieved. The exact physical qubit overhead (per logical qubit) depends on the error rate but considering state-of-the-art qubit fidelities, it will likely be a figure in excess of a hundred. QEC is then expected to take the number of required physical qubits to many thousands for economically significant algorithms and to many millions for some of the more demanding quantum computing applications. Scaling is hence a generic scientific and technological challenge. Building qubits based on the spin degree of freedom of individual electrons in silicon nanodevices offers numerous advantages over competing technologies such as the scalability of the most compact solid-state approach and the extensive industrial infrastructure of silicon transistor technology devoted to fabricating multi-billion-element integrated circuits. Besides, silicon electron spin qubits are one of the most coherent systems in nature, characteristic that has enabled demonstrating all the operational steps - initialization, control and readout - with sufficient level of precision for fault-tolerant computing. However, most of the results achieved so far come from devices fabricated in academic cleanrooms with relatively low level of reproducibility and in one- or two-qubit processors at best [Huang et al. Nature 569, 532]. But the recent demonstration of a single hole spin qubit [Maurand et al Nat Commun 7 13575] and electron spin control and readout in devices fabricated in a 300 mm complementary metal-oxide-semiconductor (CMOS) platform open an opportunity to trigger a transition from lab-based proof-of-principle experiments to manufacturing qubits at scale [Gonzalez-Zalba et al, Physics World (2019)]. In the project SiFT, I will build on my pioneering work on CMOS-based quantum computing [Nat Commun 6 6084, Nat Elect 2 236, Nat Nano 14 437] to demonstrate, for the first time, all the necessary steps to run the surface code. I will target a two-dimensional qubit lattices where arbitrary quantum errors could be detected and corrected making clusters of qubits more reliable that the individual constituents. My quantum circuit designs will be manufactured in experimental and commercial silicon foundries that use very large-scale integration processes. The project will be the steppingstone towards building in the UK a large-scale silicon-based quantum processor with sufficient error-free computational resources to make an impact on society. It will help take QC beyond NISQ into the fault-tolerant era where the computational promises of QC can be fully exploited.

So-called "resistive-switching" devices are based on nanostructured dielectric materials, in which the resistance can be varied and memorised. Arguably these devices will lead to a range of disruptive technologies in the field of infromation storage over the next 20 years. Potentially these non-volatile resistive-switching devices can have potentially high speeds, high densities, long retention times and high endurance which will drastically enhance the performance of non-volatile memories and also revolutionise the computer architectures. This research sets out to understand the property - process - structure relationships of oxide dielectrics with programmable resistance. A combination of modelling, synthesis and characterisation will be used to advance the understanding of defects in oxide materials and their control. The aims of the proposed research are to elucidate the nature and mechanisms of the formation and migration of the defects and to explore ways to control and enhance their electrical properties for resistive-switching applications. The global market for memory devices amounts to more than $57 billion and has been projected to grow to $99 billion by 2015. Within this market, a number of existing memory technologies, (DRAM, SRAM, and NAND Flash) have inherent scaling issues to overcome beyond the next generation. The search for alternative solutions is gaining momentum and an alternative candidate is Resistive RAM which exploits the resistive-switching mechanism. The UK Electronic Systems Community employs more than 850,000 people, which constitutes approximately 3% of the UK workforce. Approximately half of this employment is found in the 30,000 enterprises whose business is overtly the provision of Electronic Systems and the technologies and capabilities they need. The rest are within businesses that occupy market sectors spanning aerospace, defence, healthcare, retail, media and education. The potential impact of this project will be the development of a new manufacturing process technology, which will have applications across these sectors in the UK. The impact in terms of new materials, chemistry, products and processes will be significant if the projeproposed objectives are realised.

The semiconductor industry has provided the devices we have enjoyed for many years, including mobile phones, personal computers, on-line banking etc. The growing functionality of these products is a result of making the components, namely transistors and memory elements, ever smaller, at the rate that in every 18 months or so the number of components in a given area has doubled, which also makes the devices run faster. The industry now runs into a fundamental roadblock in shrinking the devices further, so we need to look for a new device type which will continue to provide higher performance. One strong contender is the RRAM (resistive random access memory) which we will investigate in this project. This device can be programmed to offer either a high or low electrical resistance: that is, store a logic "0" or "1", or even with some intermediate levels in between. It can store information which will remain even after the power is turned off, as so called non-volatile. With this device, a number of disruptive developments are under intensive research world-wide. Its first potential application is to increase the speed of the non-volatile memory chip in computers by more than 10 times and provide potential for further increase in the number of components. The second is in the artificial intelligence (AI) computing which mimics the functionality of human brains. AI has been widely used by Google, Facebook, Apple, etc. RRAM has the potential to bring a breakthrough in AI by solving the density, connectivity and memory bandwidth limitations of AI hardware based on conventional devices. The third is to revolutionise the programmable computing with its smaller size and non-volatility, providing advantages for computing in data centres and Internet of Things, in which the vast amount of data will be streamed through internet and the scalability and energy efficiency provided by RRAM become critical. The behaviour of RRAM devices, however, is stochastic, meaning that a large variation occurs during the device operation. At present, the lack of systematic understanding of the variability and the missing tools for variability-aware simulation hinder the research progress in RRAM-based circuit and systems design for neuromorphic and programmable computing. In this project we will collaborate with UK's leading IC design company, ARM Holdings, and the world no.1 EDA software company, Synopsys, providing direct insight into the fundamental properties of RRAM variability and developing a predictive variability-aware product design kit (PDK) that can be directly used within commercial EDA software by designers, enabling the research and design of novel RRAM based neuromorphic and programmable computing systems. We expect this project to have a significant direct impact on the UK and global ICT industry in the forthcoming Artificial Intelligence (AI) and Internet of Things (IoT) era.

For future ICT industry, the elephant in the room is Internet of Things (IoT) and Artificial Intelligence (AI). They are driving the fourth industrial revolution that is profoundly changing how we live and interact. The main issues for IoT and AI have been identified as: power, security, and cost. This project is co-created with the industrial partners and focuses on the power issue. One of the most effective way for reducing power is by lowering the operation voltage, Vg, towards the transistor threshold voltage, Vth. This has motivated recently extensive research in near threshold voltage computing. As Vg approaches Vth, the operation window (Vg-Vth) reduces and the system will be increasingly vulnerable to instability in Vth: a small rise in Vth can effectively switch off a transistor. Instability causes faults in operation, such as read and write errors in SRAM and digital timing errors. It is a limiting factor for how low (Vg-Vth) and, in turn, how much power consumption can be reduced. One of the critical tasks for low power system optimization is to minimise operation voltage and power consumption that will deliver specified yield 'Y' in 'X' years at a temperature below 'T'. To complete this optimization, designers need a fault analysis model that gives the time evolution of the probability distribution of Vth and driving current, Id, at a given distance from their target values. The further Vth and Id depart from their target values, the more likely a circuit will fail. Despite of decades of research, a reliable fault model is still not available. Indeed, in a recent review, the lack of realistic fault model tops the list of challenges for Cognitive Computing System design. Although the need for this model is clear, even world-leading EDA suppliers and foundries cannot deliver the model and current SPICE models simply do not include Jitter. This is related to weaknesses of previous research, including statistically inconsistent bottom-up methodology, limited time window, weak model verification criterion, and the neglect of the interaction of different instability sources. The fabless UK IC-design companies are using foundries for their chip fabrication. Software is the essential bridge between designers and foundries. As there are no generally accepted realistic fault models at present, designers have to rely on adding a guard-band (design margins) obtained from empirical 'worst case guess'. This contributes to the substantial discrepancy between design and Si performance. As CMOS nodes are downscaled to nano-meter range, the stochastic spreading of device parameters increases dramatically this discrepancy, which has been identified as a major challenge for optimizing the design of low power IoT and Cognitive Computing Systems. The aim of this project is to provide the world first test-proven fault model that enables statistical, dynamic, and quantitative analysis of fault rate and in turn the optimization of low power IoT and Cognitive Computing Systems. Novel techniques and methodologies will be employed to overcome the weakness of early works, including a top-down approach to remove device selection, advanced data acquisition method for long time window, qualifying the model by prediction capability, covering the interactions between different sources of instabilities. The developed model will be tested against Si performance of real circuits together with the industrial project partners. If successful, it will deliver a paradigm shift from one-size-fit-all to application specific fault analysis and optimization, reducing power and time-to-market.

Following the Moore's law the semiconductor industry has delivered continuous increase of systems functionality and speed over the last 50 years through the aggressive downscaling of the transistors. In the last 20 years the UK IC-design based industry has grown to a level of national and international importance. While IC designers in the past enjoyed the freedom that all transistors in a chip could be treated identically, this is no longer the case for the nano-meter sized transistors used in the present and future technologies. Statistical device-to-device variation is introduced by the discreteness of charge and granularity of matter and is inversely proportional to gate area, so that its impact on circuits increases with the reduction of transistor dimensions. When the number of logic gates in a system increases and the architecture becomes more complex, the tolerance to variability is greatly reduced. Even if two devices were identical after fabrication, they could suffer from different aging during operation, causing a time-dependent variability (TDV). TDV is becoming a major threat to the correctness of electronic systems, but there are no tools for its verification because of the lack of a complete understanding. The aim of this project is to carry out an in-depth investigation of the defects and mechanisms responsible for TDV and, based on that, to develop a test-proven TDV simulator, allowing IC designers to assess the impact of TDV on their circuits. The researchers at Glasgow University have pioneered variability simulation and the researchers at Liverpool John Moores University have specialised in experimental characterization of defects. Their highly complementary skills bring them together and make them well positioned to tackle this challenge. By working together with UK companies, the impact of their work on UK industry will be direct. The collaboration with IMEC and its industrial consortium also opens an effective impact pathway on an international scale. The successful control of TDV will deliver reliable electronic products and minimize their power consumption.