In the post-Moore's law era, innovative new technologies to accelerate scientific computing and memory devices are growing explosively, amongst which photonic memory devices have been attracting a great amount of interest and hold future promise for built-in, non-volatile memory with high density, fast switching, multifunctionality, low-energy consumption, and multilevel data storage compared to electronic memory devices. It is now timely to ensure that these new device concepts are developed alongside new sustainable processes - as it is in the introduction stage of new products that manufacturing processes can also be changed. Current manufacturing of high-resolution semiconductor devices primarily relies on photolithography as the patterning technique of choice. During the fabrication of these resist-based lithography techniques, development and lift-off steps utilize alkaline solutions and organic solvents as developers and removers. These are two of the main sources of hazardous chemical wastes . The US Environmental Protection Agency developed a waste management hierarchy, which states that the most preferred approach is source reduction and reuse, followed by recycling, energy recovery, treatment and disposal. Therefore, the development of a water-based manufacturing technique which limits the amount of hazardous chemicals at the source is essential to the minimization of chemical wastes. This will lead to higher resource efficiency and more efficient recycling and recovery of processing waste. That is precisely what this proposal will target. The vision is to develop facile, inexpensive, scalable solvent-free lithography for nanomanufacturing, which eliminates solvents in as many lithography processes as possible but doing this in a reliable and functionally enabling manner.

People can often see these days adverts on media company vans like "Grab your life by the Gigabits" (Virgin Media). Similar slogans appear on IT company flyers offering data analysis at Tera operations per second. They show the undeniable progress in technology, though still rarely we see performance growth per energy, for example Gigabits per Joule. And yet we are increasingly having to face with rising energy bills. As appetites for extending our intelligence wider and deeper into our everyday life steadily grow the grand challenge of ICT in making intelligence energy efficient becomes more and more evident. A significant role in this belongs to the research that aims at finding better methods for machine learning and data classification where both power and time for performing key operations in learning are reduced. In simple terms reducing power amounts to reducing average switching activity of electronic hardware, while reducing time means determining the moments when the learning actions have reached the state of sufficient quality. Self-time hardware, which works on the event-driven principles, in combination with novel machine learning methods, based on efficient approximation and Boolean logic as opposed to heavy arithmetic, gives this research a lever of innovation and potential impact against the state of the art. This project will investigate opportunities for improving performance and energy efficiency in artificial intelligence hardware created by the inherent time and power elasticity of self-timed circuits. The project will lay foundation to a new design methodology for building electronic devices and systems with machine learning (ML) capabilities at the micro- and nano-scale granularity. Those devices will be widely leveraged in many at-the-edge applications such as environmental sensors, traffic monitors, wearables, as well potential commodity ML-enhanced devices that can be used as building blocks in computer systems of the future. Micro- and nanoclassifiers and decision makers that can operate in real-time with power/energy efficiency are expected to find many 'light-weight' applications, so optimal (in terms of latency and energy) control is crucial. Here is an example of handwritten character recognition by an electronic pen with energy-harvested power. A reference class is given (e.g., digit "5"). Then, a few attempts in handwriting of digit 5 are made. During all these attempts training is performed. Then another reference class is given, and similar training is performed on it, and so on. The key requirements are to keep time spent limited and consumed energy minimised. Training is to be done to the best of the achievable accuracy. There are several trade-offs involved between speed and power and accuracy of learning. The success of the project will be measured in terms of the answers to the key research questions about the dynamics of machine learning in self-timed circuits; for example, whether the asynchronous design approach combined with the use of learning automata and logic-based inference will reach minimum energy point for a given machine learning problem. The project outcomes in theory and design methodology will be validated by means of extensive simulations, prototyping, IC fabrication and testing, and, ultimately, via an embodiment of the new hardware solutions into a concrete IoT application. A particularly challenging and breaking through validation will be the development and fabrication of the first asynchronous machine learning integrated circuit using flexible substrates. The practical impact of this research will be in the directions and methods of designing intelligent embedded electronics that will be capable of performing run-time classification of data obtained from environmental sensors, audio and image signals, as well as fast moving consumer goods (FMCG) and smart packaging using flexible IC technology.

Concerted progress in energy sources, sensing, and communications are bringing closer a future in which connected smart sensors will contribute to improved health and sustainable use of resources via environmental, personal health, and process monitoring. For maximum value, data should be generated and processed through means that are reliable, but also cost effective, energy efficient, and ecologically sound. By doing the initial conditioning and processing of incoming data close to the sensor (i.e. at the edge of a sensing network), energy savings and signal integrity can be improved, at the expense of local complexity. The electronic devices performing signal conditioning, data conversion, and decision in such systems are typically realised in state-of-the art and exorbitantly expensive chip manufacturing facilities (fabs). Recent pressure on the chip supply chain has increased the appeal of exploring alternative technologies. Chief among these are thin-film processes in which electronic devices and sensing components can be manufactured at a fraction of the cost, but simultaneously with: a major drop in performance; challenges in manufacturing circuits of the required complexity; and in many cases, much higher energy requirements during operation. At Surrey, we have devised and are developing a design philosophy and associated thin-film electronic device called the source-gated transistor (SGT), with superior power efficiency, stability, and amplification compared to conventional thin-film transistors, advantages which come at the cost of further reducing the operating speed. Our recent observation shows that the best SGT performance arises when combining thin semiconductor materials of high electrical permittivity with low-permittivity dielectrics, in a design that is counterintuitive to traditional approaches but is consistent with first principles. In this project, we will demonstrate SGTs and circuits, with hitherto inaccessible levels of performance and energy efficiency, by combining the advantages of the device architecture with the material properties of suspended crystalline silicon and germanium membranes. The charge carrier mobility of these materials, vastly superior to the usual thin films, and the geometrical scaling afforded by the exceptional SGT functional features, will enable circuits that are >100x faster and >10x more energy efficient than previous SGT-based designs. By expressly merging thin-film and "traditional silicon"-based approaches, these devices will serve as unique building blocks for highly efficient wearable, point-of-care, and distributed sensing systems with built-in sensing, signal conditioning, and decision. Even as we will be using materials aligned with traditional chips, our approach will not rely on the costly state-of-the art fabrication facilities, relieving much needed manufacturing capacity for complex chips e.g. processors and AI accelerators, while delivering transformative functionality to an emerging sensor ecosystem. In this initial project, the route to manufacturing will be explored, but as a secondary concern. We will focus primarily on the demonstration of a ground-breaking concept, through innovative joining of previously disparate materials and fabrication philosophies. In a high-risk, high-reward approach, we will confirm transistor operation, not only as amplifiers and signal conditioning stages, but potentially as sensors for bio-, chemical and mechanical stimuli. We will establish design rules and guidelines, supported by numerical simulation and by material and device characterisation. Thus, these advances will holistically represent a toolkit for the implementation of highly versatile, multipurpose sensing and processing systems towards a connected future beyond the Internet-of-Things. As a catalyst for prolific academic and industrial advances, the research will contribute firmly to maintaining the UK's leadership in emerging electronic technologies.

Over the last 40 years, we have seen a transformation in how we use electronic devices in our everyday lives from the emergence of home computing in the 1980s with occasional 'dial-up' connection of a single device in the home to the internet. In contrast, today we have a plethora of smart devices such as televisions, speakers, white goods, central heating and even doorbells all continuously connected to the internet through high speed broadband in addition to our mobile phones, tablets and personal computers. This trend will continue, with smart packaging, ubiquitous environmental monitoring, wearable wellbeing monitors amongst other emerging technologies becoming commonplace. The development of this 'Internet of Things' portents new manufacturing challenges. Silicon-based electronics has developed over this time based on trying to minimise the cost per transistor in electronic components such as microprocessors. In this way, microprocessors can be fabricated with billions of transistors at an affordable cost point. However, it is just not appropriate to use silicon-based electronics for all of these emerging applications because of cost, form factor, environmental and other limitations. Large-area electronics (LAE) is the field which sees the use of new materials and processes to make electronics where the cost per unit area is minimised rather than the cost per device. Displays are perhaps the best known example of LAE, where a layer of electronics sits over an entire screen controlling the light output from each pixel, but other areas are emerging, and in particular the development of basic microprocessors, memories and logic on substrates such as flexible plastics which have radically different form factors from silicon. Also, as the cost of manufacture is much lower than for silicon-based electronics, manufacturing in the UK is a reality. As with silicon, decreasing the physical size of LAE devices leads to performance enhancements, and these will be needed for future generations of smart technologies. but in general the cost of manufacture increases as feature size is reduced, and this makes fabrication at the nanoscale prohibitively expensive. We have been working on a patterning technique called Adhesion Lithography (A-Lith). This allows the reproducible fabrication of gaps ~10 nm in length to be formed between adjacent metal electrodes using only low resolution patterning of the metal electrodes themselves. We have published the design of a tool to do this at https://doi.org/10.17863/CAM.68204 . However, to make an electronic device such as a transistor, we need to put materials into the gap between these metal electrodes. Nanomaterials, such as carbon nanotubes, silicon nanowires, zinc oxide nanowires and graphene, have been shown to have exceptional intrinsic electronic properties as a result of their nanostructure. However, the challenge is usually to put metal electrodes onto these materials to be able to make use of these properties. In this work, we propose to develop the manufacturing processes to bring together A-Lith nanogap manufacture with the bottom-up growth of these nanomaterials so that they naturally grow across the nanogap to make a new generation of electronic devices at low cost. Two such 'nanomaterial-in-nanogap' devices which we will demonstrate are transistors and memristors. The former have been the building block behind traditional electronic circuits. The latter are seen as the building block behind the neuromorphic electronics of the future, where we create electronic devices which take inspiration from the synapses of the brain to operate. This project aims to bring the manufacture of these new nanomaterial-in-nanogap devices for large-area electronics to reality.

Like graphene, a layer of a transition metal dichalcogenide (TMDC), ME2 (where M = transition metal and E = sulfur, selenium or tellurium), consists of a single- or few-atom-thick, covalently bonded lattice. These atomic sheets exhibit extraordinary electronic and optical properties, as they do not suffer from dangling bonds and trap states at the surface. The van der Waals interactions between the layers allows the integration of very different materials without the constraints of crystal lattice matching. Moreover, those few layers can withstand mechanical strains of 10%, which makes these materials particularly suitable for flexible electronic devices, a market expected to be worth more than £10B in the next five years. Heterostructures of 2D materials and graphene have great potential for various electronic, opto-electronic, energy, and sensor applications but are held back by technological limitations. It is the intention of this proposal to take advantage of our recent breakthroughs in electrodeposition of few layer 2D chalcogenides, such as MoS2 and WS2, on metal as well graphene electrodes. We will demonstrate these advantages through a variety of devices which combine state-of-the-art performance together with scalable, industrially acceptable processing on flexible substrates. Working with our project partners we will aim to maximise the potential societal and economic impacts that emerge from this work.